Low subthreshold slope in junctionless multigate transistors

The improvement of subthreshold slope due to impact ionization is compared between ""standard"" inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3358131]

Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short- channel devices down to 30 nm at different temperatures have been also used to validate the model.

The zero temperature coefficient in junctionless nanowire transistors

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows that ZTC may occur in JNTs depending mainly on the series resistance of the devices and its dependence on the temperature. Experimental results of drain current, threshold voltage, and series resistance are presented for both long and short channel n and p-type devices. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4744965]