Junctionless 6T SRAM cell

.The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 mA along with a low leakage current of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pullup ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.