Implementation of parallel tridiagonal solvers for a heterogeneous computing environment

Tridiagonal diagonally dominant linear systems arise in many scientific and engineering applications. The standard Thomas algorithm for solving such systems is inherently serial forming a bottleneck in computation. Algorithms such as cyclic reduction and SPIKE reduce a single large tridiagonal system into multiple small independent systems which can be solved in parallel. We have developed portable cyclic reduction and SPIKE algorithm OpenCL implementations with the intent to target a range of co-processors in a heterogeneous computing environment including Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and other multi-core processors. In this paper, we evaluate these designs in the context of solver performance, resource efficiency and numerical accuracy.

Enhancing skill acquisition and expertise in high performance programmes

Our research programme with elite athletes has investigated and implemented learning design from an ecological dynamics perspective, examining its effects on movement coordination and control and the acquisition of expertise. Ecological dynamics is a systemsoriented theoretical rationale for understanding the emergent relations in a complex system formed by each performer and a performance environment. This approach has identified the individual-environment relationship as the relevant scale of analysis for modelling how processes of perception, cognition and action underpin expert performance in sport (Davids et al., 2014; Zelaznik, 2014). In this chapter we elucidate key concepts from ecological dynamics and exemplify how they have informed our understanding of relevant psychological processes including: movement coordination and its acquisition, learning and transfer, impacting on practice task design in high performance programmes.

Use of a volatile buffer at ambient temperature *1: Versatile approach to the purification of self-complementary synthetic deoxyoligonucleotides by reversed-phase high-performance liquid chromatography

Abstract is not available.

Refractory boron compounds for high performance: Theory and experiment

We have shown that novel synthesis methods combined with careful evaluation of DFT phonon calculations provides new insight into boron compounds including a capacity to predict Tc for AlB2-type superconductors.

Natural convection in rectangular cavities at high Rayleigh number

Natural convection in rectangular two-dimensional cavities with differentially heated side walls is a standard problem in numerical heat transfer. Most of the existing studies has considered the low Ra laminar regime. The general thrust of the present research is to investigate higher Ra flows extending into the unsteady and turbulent regimes where the physics is not fully understood and appropriate models for turbulence are not yet established. In the present study the Boussinesq approximation is being used, but the theoretical background and some preliminary results have been obtained[1] for flows with variable properties.

A heterogeneous computing approach to simulation of the Heston Stochastic Volatility Model

Stochastic volatility models are of fundamental importance to the pricing of derivatives. One of the most commonly used models of stochastic volatility is the Heston Model in which the price and volatility of an asset evolve as a pair of coupled stochastic differential equations. The computation of asset prices and volatilities involves the simulation of many sample trajectories with conditioning. The problem is treated using the method of particle filtering. While the simulation of a shower of particles is computationally expensive, each particle behaves independently making such simulations ideal for massively parallel heterogeneous computing platforms. In this paper, we present our portable Opencl implementation of the Heston model and discuss its performance and efficiency characteristics on a range of architectures including Intel cpus, Nvidia gpus, and Intel Many-Integrated-Core (mic) accelerators.

High-performance graphene-based supercapacitors made by a scalable blade-coating approach

Graphene oxide (GO) sheets can form liquid crystals (LCs) in their aqueous dispersions that are more viscous with a stronger LC feature. In this work we combine the viscous LC-GO solution with the blade-coating technique to make GO films, for constructing graphene-based supercapacitors in a scalable way. Reduced GO (rGO) films are prepared by wet chemical methods, using either hydrazine (HZ) or hydroiodic acid (HI). Solid-state supercapacitors with rGO films as electrodes and highly conductive carbon nanotube films as current collectors are fabricated and the capacitive properties of different rGO films are compared. It is found that the HZ-rGO film is superior to the HI-rGO film in achieving high capacitance, owing to the 3D structure of graphene sheets in the electrode. Compared to gelled electrolyte, the use of liquid electrolyte (H2SO4) can further increase the capacitance to 265 F per gram (corresponding to 52 mF per cm2) of the HZ-rGO film.

Atomic layer-by-layer Co3O4/graphene composite for high performance lithium-ion batteries

An "atomic layer-by-layer" structure of Co3O4/graphene is developed as an anode material for lithium-ion batteries. Due to the atomic thickness of both the Co3O4 nanosheets and the graphene, the composite exhibits an ultrahigh specific capacity of 1134.4 mAh g-1 and an ultralong life up to 2000 cycles at 2.25 C, far beyond the performances of previously reported Co3O4/C composites.

Dual yolk-shell structure of carbon and silica-coated silicon for high-performance lithium-ion batteries

Silicon batteries have attracted much attention in recent years due to their high theoretical capacity, although a rapid capacity fade is normally observed, attributed mainly to volume expansion during lithiation. Here, we report for the first time successful synthesis of Si/void/SiO2/void/C nanostructures. The synthesis strategy only involves selective etching of SiO2 in Si/SiO2/C structures with hydrofluoric acid solution. Compared with reported results, such novel structures include a hard SiO2-coated layer, a conductive carbon-coated layer, and two internal void spaces. In the structures, the carbon can enhance conductivity, the SiO2 layer has mechanically strong qualities, and the two internal void spaces can confine and accommodate volume expansion of silicon during lithiation. Therefore, these specially designed dual yolk-shell structures exhibit a stable and high capacity of 956 mA h g−1 after 430 cycles with capacity retention of 83%, while the capacity of Si/C core-shell structures rapidly decreases in the first ten cycles under the same experimental conditions. The novel dual yolk-shell structures developed for Si can also be extended to other battery materials that undergo large volume changes.

A novel ionic diffusion strategy to fabricate high-performance anode-supported solid oxide fuel cells (SOFCs) with proton-conducting Y-doped BaZrO3 films

A stable Y-doped BaZrO3 electrolyte film, which showed a good performance in proton-conducting SOFCs, was successfully fabricated using a novel ionic diffusion strategy.

Process makes perfect: High-performance design creates healthy environments for high-performance learning

Considering the staggering benefits of high-performance schools, it seems an obvious choice to “go green.” High-performance schools offer an exceptionally cost-effective means to enhance student learning, using on average 33 percent less energy than conventionally designed schools, and provide substantial health gains, including reduced respiratory problems and absenteeism. According to the 2006 study, Greening America's Schools, Costs and Benefits, co-sponsored by the American Institute of Architects (AIA) and Capital E, a green building consulting firm, high-performance lighting is a key element of healthy learning environments, contributing to improved test scores, reduced off-task behavior, and higher achievement among students. Few argue this point more convincingly than architect Heinz Rudolf, of Portland-Oregon-based Boora Architects, who has designed sustainable schools for more than 80 school districts in Oregon, Washington, Colorado, and Wyoming, and has pioneered the high-performance school movement. Boora's recently completed project, the Baker Prairie Middle School in Canby, Oregon is one of the most sustainable K-12 facilities in the state, and illustrates Rudolf's progressive and research-intensive approach to school design.

HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

In this letter, we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of an HEMT and a FinFET, to obtain excellent performance and good OFF-state control. Followed by the description of the design, 3-D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and nonplanar Si n-MOSFET data of comparable gate length using standard benchmarking techniques.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well