Continuity equation based nonquasi-static charge model for independent double gate MOSFET

Using the numerical device simulation we show that the relationship between the surface potentials along the channel in any double gate (DG) MOSFET remains invariant in QS (quasistatic) and NQS (nonquasi-static) condition for the same terminal voltages. This concept along with the recently proposed `piecewise charge linearization' technique is then used to develop the intrinsic NQS charge model for a Independent DG (IDG) MOSFET by solving the governing continuity equation. It is also demonstrated that unlike the usual MOSFET transcapacitances, the inter-gate transcapacitance of a IDG-MOSFET initially increases with the frequency and then saturates, which might find novel analog circuit application. The proposed NQS model shows good agreement with numerical device simulations and appears to be useful for efficient circuit simulation.

Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Secure Transmission in Cooperative Networks with Weak Eavesdroppers

In this letter, we propose a scheme to improve the secrecy rate of cooperative networks using Analog Network Coding (ANC). ANC mixes the signals in the air; the desired signal is then separated out, from the mixed signals, at the legitimate receiver using techniques like self interference subtraction and signal nulling, thereby achieving better secrecy rates. Assuming global channel state information, memoryless adversaries and the decode-and-forward strategy, we seek to maximize the average secrecy rate between the source and the destination, subject to an overall power budget. Then, exploiting the structure of the optimization problem, we compute its optimal solution. Finally, we use numerical evaluations to compare our scheme with the conventional approaches.

Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.

Load Balancing with Availability Checker and Load Reporters (LB-ACLRs) for improved Performance in Distributed Systems

Distributed system has quite a lot of servers to attain increased availability of service and for fault tolerance. Balancing the load among these servers is an important task to achieve better performance. There are various hardware and software based load balancing solutions available. However there is always an overhead on Servers and the Load Balancer while communicating with each other and sharing their availability and the current load status information. Load balancer is always busy in listening to clients' request and redirecting them. It also needs to collect the servers' availability status frequently, to keep itself up-to-date. Servers are busy in not only providing service to clients but also sharing their current load information with load balancing algorithms. In this paper we have proposed and discussed the concept and system model for software based load balancer along with Availability-Checker and Load Reporters (LB-ACLRs) which reduces the overhead on server and the load balancer. We have also described the architectural components with their roles and responsibilities. We have presented a detailed analysis to show how our proposed Availability Checker significantly increases the performance of the system.

Design and commissioning of a 30kw direct drive wave generator

The Trident Energy TE5 is a prototype wave energy converter operating on the principle of having direct-drive linear generators mounted above the water surface, coupled to floats moving under the rig deck. This paper describes aspects of the TE5 design, including its generators, power electronic systems and the conception of its marine structure.

The design structure system - A method for managing the design of complex systems

Systems design involves the determination of interdependent variables. Thus the precedence ordering for the tasks of determining these variables involves circuits. Circuits require planning decisions abut how to iterate and where to use estimates. Conventional planning techniques, such as critical path, do not deal with these problems. Techniques are shown in this paper which acknowledge these circuits in the design of systems. These techniques can be used to develop an effective engineering plan, showing where estimates are to be used, how design iterations and reviews are handled, and how information flows during the design work.

Biomimetics in design-oriented information systems research

Modern information systems (ISs) are becoming increasingly complex. Simultaneously, organizational changes are occurring more often and more rapidly. Therefore, emergent behavior and organic adaptivity are key advantages of ISs. In this paper, a design science research (DSR) question for design-oriented information systems research (DISR) is proposed: Can the application of biomimetic principles to IS design result in the creation of value by innovation? Accordingly, the properties of biological IS are analyzed, and these insights are crystallized into a theoretical framework to address the three major aspects of biomimetic ISs: user experience, information processing, and management cybernetics. On this basis, the research question is elaborated together with a starting point for a research methodology in biomimetic information systems.

Flo/Stress: an integrated software module to predict stress in electronic products

Software technology that predicts stress in electronic systems and packages, developed as part of TCS Programme, is described. The software is closely integrated within a thermal design tool providing the ability to simulate the coupled effects of airflow, temperature and stress on product performance. This integrated approach to analysis will help decrease the number of design cycles.

Turbulence modelling and its impact on CFD predictions for cooling of electronic components

This paper will discuss Computational Fluid Dynamics (CFD) results from an investigation into the accuracy of several turbulence models to predict air cooling for electronic packages and systems. Also new transitional turbulence models will be proposed with emphasis on hybrid techniques that use the k-ε model at an appropriate distance away from the wall and suitable models, with wall functions, near wall regions. A major proportion of heat emitted from electronic packages can be extracted by air cooling. This flow of air throughout an electronic system and the heat extracted is highly dependent on the nature of turbulence present in the flow. The use of CFD for such investigations is fast becoming a powerful and almost essential tool for the design, development and optimization of engineering applications. However turbulence models remain a key issue when tackling such flow phenomena. The reliability of CFD analysis depends heavily on the turbulence model employed together with the wall functions implemented. In order to resolve the abrupt fluctuations experienced by the turbulent energy and other parameters located at near wall regions and shear layers a particularly fine computational mesh is necessary which inevitably increases the computer storage and run-time requirements. The PHYSICA Finite Volume code was used for this investigation. With the exception of the k-ε and k-ω models which are available as standard within PHYSICA, all other turbulence models mentioned were implemented via the source code by the authors. The LVEL, LVEL CAP, Wolfshtein, k-ε, k-ω, SST and kε/kl models are described and compared with experimental data.

Design of silicon IP cores for biorthogonal wavelet transforms

A methodology for rapid silicon design of biorthogonal wavelet transform systems has been developed. This is based on generic, scalable architectures for the forward and inverse wavelet filters. These architectures offer efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation and interpolation. The resulting designs have been parameterised in terms of types of wavelet and wordlengths for data and coefficients. Control circuitry is embedded within these cores that allows them to be cascaded for any desired level of decomposition without any interface logic. The time to produce silicon designs for a biorthogonal wavelet system is only the time required to run synthesis and layout tools with no further design effort required. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. These designs are also portable across a range of foundries and are suitable for FPGA and PLD implementations.