Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems


Autoria(s): Reddy, Brijesh P; Srinivasa, Shayan Garani; Dahandeh, Shafa
Data(s)

2015

Resumo

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/51783/1/IEEE_Tra_on_Mag_51-4_2015.pdf

Reddy, Brijesh P and Srinivasa, Shayan Garani and Dahandeh, Shafa (2015) Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems. In: 25th Magnetic Recording Conference (TMRC), AUG 11-14, 2014, Berkeley, CA.

Publicador

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Relação

http://dx.doi.org/ 10.1109/TMAG.2014.2361619

http://eprints.iisc.ernet.in/51783/

Palavras-Chave #Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Tipo

Conference Proceedings

NonPeerReviewed