Fin-Enabled-Area-Scaled Tunnel FET
Data(s) |
2015
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Resumo |
While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements. |
Formato |
application/pdf |
Identificador |
http://eprints.iisc.ernet.in/52587/1/IEEE_Tra_on_Ele_Dev_62-10_3184_2015.pdf Hemanjaneyulu, Kuruva and Shrivastava, Mayank (2015) Fin-Enabled-Area-Scaled Tunnel FET. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 62 (10). pp. 3184-3191. |
Publicador |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Relação |
http://dx.doi.org/10.1109/TED.2015.2469678 http://eprints.iisc.ernet.in/52587/ |
Palavras-Chave | #Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology) |
Tipo |
Journal Article PeerReviewed |