Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness


Autoria(s): Gupta, Ankur; Shrivastava, Mayank; Baghini, Maryam Shojaei; Chandorkar, AN; Gossner, Harald; Rao, Ramgopal V
Data(s)

2015

Resumo

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/52586/1/IEEE_Tra_on_Ele_Dev_62-10_3176_2015.pdf

Gupta, Ankur and Shrivastava, Mayank and Baghini, Maryam Shojaei and Chandorkar, AN and Gossner, Harald and Rao, Ramgopal V (2015) Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 62 (10). pp. 3176-3183.

Publicador

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Relação

http://dx.doi.org/10.1109/TED.2015.2470109

http://eprints.iisc.ernet.in/52586/

Palavras-Chave #Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Tipo

Journal Article

PeerReviewed