Part I: High-Voltage MOS Device Design for Improved Static and RF Performance
Data(s) |
2015
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Resumo |
In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device. |
Formato |
application/pdf |
Identificador |
http://eprints.iisc.ernet.in/52585/1/IEEE_Tra_on_Ele_Dev_62-10_3168_2015.pdf Gupta, Ankur and Shrivastava, Mayank and Baghini, Maryam Shojaei and Sharma, Dinesh Kumar and Gossner, Harald and Rao, Ramgopal V (2015) Part I: High-Voltage MOS Device Design for Improved Static and RF Performance. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 62 (10). pp. 3168-3175. |
Publicador |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Relação |
http://dx.doi.org/10.1109/TED.2015.2470117 http://eprints.iisc.ernet.in/52585/ |
Palavras-Chave | #Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology) |
Tipo |
Journal Article PeerReviewed |