Molecular Computational Elements Encode Large Populations of Small Objects

Since the introduction of molecular computation1, 2, experimental molecular computational elements have grown3, 4, 5 to encompass small-scale integration6, arithmetic7 and games8, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size9 (about 1 nm) and large 'on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100 m) used for synthesis of combinatorial libraries10, 11. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a 'wash and watch' protocol12. Our focus on converting molecular science into technology concerning analog sensors13, 14, turns to digital logic devices in the present work.

Reuseable Silicon IP Cores for Discrete Wavelet Transform Applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.

Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Efficient quantum computation using coherent states

We study universal quantum computation using optical coherent states. A teleportation scheme for a coherent-state qubit is developed and applied to gate operations. This scheme is shown to be robust to detection inefficiency.

Vibrational coherent quantum computation

A long-lived coherent state and nonlinear interaction have been experimentally demonstrated for the vibrational mode of a trapped ion. We propose an implementation of quantum computation using coherent states of the vibrational modes of trapped ions. Differently from earlier experiments, we consider a far-off resonance for the interaction between external fields and the ion in a bidimensional trap. By appropriate choices of the detunings between the external fields, the adiabatic elimination of the ionic excited level from the Hamiltonian of the system allows for beam splitting between orthogonal vibrational modes, production of coherent states, and nonlinear interactions of various kinds. In particular, this model enables the generation of the four coherent Bell states. Furthermore, all the necessary operations for quantum computation, such as preparation of qubits and one-qubit and controlled two-qubit operations, are possible. The detection of the state of a vibrational mode in a Bell state is made possible by the combination of resonant and off-resonant interactions between the ion and some external fields. We show that our read-out scheme provides highly efficient discrimination between all the four Bell states. We extend this to a quantum register composed of many individually trapped ions. In this case, operations on two remote qubits are possible through a cavity mode. We emphasize that our remote-qubit operation scheme does not require a high-quality factor resonator: the cavity field acts as a catalyst for the gate operation.

Non-local quantum gates: a cavity-quantum-electrodynamics implementation

The problems related to the management of large quantum registers could be handled in the context of distributed quantum computation: unitary non-local transformations among spatially separated local processors are realized performing local unitary transformations and exchanging classical communication. In this paper, a scheme is proposed for the implementation of universal non-local quantum gates such as a controlled NOT (CNOT) and a controlled quantum phase gate (CQPG). The system chosen for their physical implementation is a cavity-quantum-electrodynamics (CQED) system formed by two spatially separated microwave cavities and two trapped Rydberg atoms. The procedures to follow for the realization of each step necessary to perform a specific non-local operation are described.

Quantum-information processing with noisy cluster states

We provide an analysis of basic quantum-information processing protocols under the effect of intrinsic nonidealities in cluster states. These nonidealities are based on the introduction of randomness in the entangling steps that create the cluster state and are motivated by the unavoidable imperfections faced in creating entanglement using condensed-matter systems. Aided by the use of an alternative and very efficient method to construct cluster-state configurations, which relies on the concatenation of fundamental cluster structures, we address quantum-state transfer and various fundamental gate simulations through noisy cluster states. We find that a winning strategy to limit the effects of noise is the management of small clusters processed via just a few measurements. Our study also reinforces recent ideas related to the optical implementation of a one-way quantum computer.

Natural three-qubit interactions in one-way quantum computing

We address the effects of natural three-qubit interactions on the computational power of one-way quantum computation. A benefit of using more sophisticated entanglement structures is the ability to construct compact and economic simulations of quantum algorithms with limited resources. We show that the features of our study are embodied by suitably prepared optical lattices, where effective three-spin interactions have been theoretically demonstrated. We use this to provide a compact construction for the Toffoli gate. Information flow and two-qubit interactions are also outlined, together with a brief analysis of relevant sources of imperfection.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression

This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.

2.4 GHz Class-E power amplifier with transmissionline harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.