Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm


Autoria(s): McLoone, Maire
Data(s)

01/10/2005

Resumo

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Identificador

http://pure.qub.ac.uk/portal/en/publications/hardware-performance-analysis-of-the-shacal2-encryption-algorithm(2a7cc856-ebfb-4ee5-8ab2-0e03906ef215).html

http://dx.doi.org/10.1049/ip-cds:20059027

http://www.scopus.com/inward/record.url?scp=27544502935&partnerID=8YFLogxK

Idioma(s)

eng

Direitos

info:eu-repo/semantics/restrictedAccess

Fonte

McLoone , M 2005 , ' Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm ' IEE Proceedings - Circuits, Devices and Systems , vol 152 (5) , no. 5 , pp. 478-484 . DOI: 10.1049/ip-cds:20059027

Palavras-Chave #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering
Tipo

article