A nanowire magnetic memory cell based on a periodic magnetic superlattice

We analyse the operation of a semiconductor nanowire-based memory cell. Large changes in the nanowire conductance result when the magnetization of a periodic array of nanoscale magnetic gates, which comprise the other key component of the memory cell, is switched between distinct configurations by an external magnetic field. The resulting conductance change provides the basis for a robust memory effect, which can be implemented in a semiconductor structure compatible with conventional semiconductor integrated circuits.

Electron beam and laser testing on the novel stripixel detectors

The novel Si stripixel detector, developed at BNL (Brookhaven National Laboratory), has been applied in the development of a prototype Si strip detector system for the PHENIX Upgrade at RHIC. The Si stripixel detector can generate X-Y two-dimensional (2D) position sensitivity with single-sided processing and readout. Test stripixel detectors with pitches of 85 and 560 mu m have been subjected to the electron beam test in a SEM set-up, and to the laser beam test in a lab test fixture with an X-Y-Z table for laser scanning. Test results have shown that the X and Y strips are well isolated from each other, and 2D position sensitivity has been well demonstrated in the novel stripixel detectors. (c) 2005 Elsevier B.V. All rights reserved.

Memory effect in a system of zincblende Mn-rich Mn(Ga)As nanoclusters embedded in GaAs

Zincblende Mn-rich Mn(Ga)As nanoclusters embedded in GaAs matrices are fabricated by in situ postgrowth annealing diluted magnetic semiconductor (Ga,Mn)As films with Mn concentration ranging from 2.6% to 8% at 650 degrees C. Magnetization measurements show that memory effect and slow magnetic relaxation, the typical characteristics of the spin-glass-like phase, occur below the blocking temperature of 45 K in samples with high Mn concentration, while for samples with low Mn concentration, ferromagnetic order remains up to 360 K. The behavior of low-temperature spin dynamics can be explained by the hierarchical model. (c) 2007 American Institute of Physics.

A time-varying controllable fault-tolerant field associative memory model and its simulation

A time-varying controllable fault-tolerant field associative memory model and the realization algorithms are proposed. On the one hand, this model simulates the time-dependent changeability character of the fault-tolerant field of human brain's associative memory. On the other hand, fault-tolerant fields of the memory samples of the model can be controlled, and we can design proper fault-tolerant fields for memory samples at different time according to the essentiality of memory samples. Moreover, the model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. And the fault-tolerant fields of the memory samples are full of the whole real space R-n. The simulation shows that the model has the above characters and the speed of associative memory about the model is faster.

The design algorithm of an associative memory neural network

A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.

Study on Mg memory effect in npn type AlGaN/GaN HBT structures grown by MOCVD

AlGaN/GaN npn heterojunction bipolar transistor structures were grown by low-pressure MOCVD. Secondary ion mass spectroscopy (SIMS) measurements were carried out to study the Mg memory effect and redistribution in the emitter-base junction. The results indicated that there is a Mg-rich film formed in the ongrowing layer after the Cp2Mg source is switched off. The Mg-rich film can be confined in the base section by switching off the Cp2Mg source for appropriate time before the end of base growth. Low temperature growth of the undoped GaN spacer suppresses the Mg redistribution from Mg rich film. The delay rate of the Mg profile in sample C with spacer growing in low temperature is about 56 nm/decade, which becomes sharper than 80 nm/decade of the samples A and B without low temperature spacer. (C) 2005 Elsevier Ltd. All rights reserved.

Photon-storage in optical memory cells based on a semiconductor quantum dot-quantum well hybrid structure

We report a new type of photonic memory cell based on a semiconductor quantum dot (QD)-quantum well (QW) hybrid structure, in which photo-generated excitons can be decomposed into separated electrons and holes, and stored in QW and QDs respectively. Storage and retrieval of photonic signals are verified by time-resolved photoluminescence experiments. A storage time in excess of 100ms has been obtained at a temperature of 10 K while the switching speed reaches the order of ten megahertz.

Design, simulation and testing of large area silicon drift detectors and detector array for X-ray spectroscopy

Large area (25 mm(2)) silicon drift detectors and detector arrays (5x5) have been designed, simulated, and fabricated for X-ray spectroscopy. On the anode side, the hexagonal drift detector was designed with self-biasing spiral cathode rings (p(+)) of fixed resistance between rings and with a grounded guard anode to separate surface current from the anode current. Two designs have been used for the P-side: symmetric self-biasing spiral cathode rings (p(+)) and a uniform backside p(+) implant. Only 3 to 5 electrodes are needed to bias the detector plus an anode for signal collection. With graded electrical potential, a sub-nanoamper anode current, and a very small anode capacitance, an initial FWHM of 1.3 keV, without optimization of all parameters, has been obtained for 5.9 keV Fe-55 X-ray at RT using a uniform backside detector.

In-Situ Boron and Aluminum Doping and Their Memory Effects in 4H-SiC Homoepitaxial Layers Grown by Hot-Wall LPCVD

The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52x10(20) cm(-3) with Hall mobility of about 1 cm(2)/Vs and resistivity of 1.6 similar to 2.2x10(-2) Omega cm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Omega cm for resistivity, 5.3x10(18) cm(-3) for hole carrier concentration, and 7 cm(2)/VS for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Fully lithography independent fabrication of nanogap electrodes for lateral phase-change random access memory application

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an efficient method to generate feasible paths for basis path testing

Basis path testing is a very powerful structural testing criterion. The number of test paths equals to the cyclomatic complexity of program defined by McCabe. Traditional test generation methods select the paths either without consideration of the constraints of variables or interactively. In this note, an efficient method is presented to generate a set of feasible basis paths. The experiments show that this method can generate feasible basis paths for real-world C programs automatically in acceptable time.