994 resultados para Hardware Solver


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The Mathematica system (version 4.0) is employed in the solution of nonlinear difusion and convection-difusion problems, formulated as transient one-dimensional partial diferential equations with potential dependent equation coefficients. The Generalized Integral Transform Technique (GITT) is first implemented for the hybrid numerical-analytical solution of such classes of problems, through the symbolic integral transformation and elimination of the space variable, followed by the utilization of the built-in Mathematica function NDSolve for handling the resulting transformed ODE system. This approach ofers an error-controlled final numerical solution, through the simultaneous control of local errors in this reliable ODE's solver and of the proposed eigenfunction expansion truncation order. For covalidation purposes, the same built-in function NDSolve is employed in the direct solution of these partial diferential equations, as made possible by the algorithms implemented in Mathematica (versions 3.0 and up), based on application of the method of lines. Various numerical experiments are performed and relative merits of each approach are critically pointed out.

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This work describes the methodology, basic procedures and instrumental employed by the Solar Energy Laboratory at Universidade Federal do Rio Grande do Sul for the determination of current-voltage characteristic curves of photovoltaic modules. According to this methodology, I-V characteristic curves were acquired for several modules under diverse conditions. The main electrical parameters were determined and the temperature and irradiance influence on photovoltaic modules performance was quantified. It was observed that most of the tested modules presented output power values considerably lower than those specified by the manufacturers. The described hardware allows the testing of modules with open-circuit voltage up to 50 V and short-circuit current up to 8 A.

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The evolution of digital circuit technology, leadind to higher speeds and more reliability allowed the development of machine controllers adapted to new production systems (e.g., Flexible Manufacturing Systems - FMS). Most of the controllers are developed in agreement with the CNC technology of the correspondent machine tool manufacturer. Any alterations or adaptation of their components are not easy to be implemented. The machine designers face up hardware and software restrictions such as lack of interaction among system's elements and impossibility of adding new function. This is due to hardware incompatibility and to software not allowing alterations in the source program. The introduction of open architecture philosophy propitiated the evolution of a new generation of numeric controllers. This brought the conventional CNC technology to the standard IBM - PC microcomputer. As a consequence, the characteristics of the CNC (positioning) and the microcomputer (easy of programming, system configuration, network communication etc) are combined. Some researchers have addressed a flexible structure of software and hardware allowing changes in the hardware basic configuration and all control software levels. In this work, the development of open architecture controllers in the OSACA, OMAC, HOAM-CNC and OSEC architectures is described.

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Tämän diplomityön tavoitteena on ollut suunnitella radiaalikompressori. Aluksi on tutustuttu radiaalikompressorissa tapahtuviin ilmiöihin, jonka jälkeen radiaalikompressori on suunniteltu. Reunaehtoina suunnittelussa olivat toimilaitteelta saatava teho 250 kW ja sen suurin pyörimisnopeus 500 Hz. Esisuunnittelu on tehty Virtaustekniikan laboratoriossa kehitetyllä CentriFlow-ohjelmalla. Juoksupyörän muoto on suunniteltu viskoosittomilla 2D-malleilla. Juoksupyörän muodon suunniittelussa on käytetty kaupallista AxCent-ohjelmaa. Juoksupyörän muoto on tarkistettu laskennallisen virtausdynamiikan avulla. Virtausmallinnuksessa käytettiin FinFlo-ohjelmaa. Suunnittelun ja mallinnuksen pohjalta valittiin kolme erilaista juoksupyörää valmistukseen.

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The capabilities and thus, design complexity of VLSI-based embedded systems have increased tremendously in recent years, riding the wave of Moore’s law. The time-to-market requirements are also shrinking, imposing challenges to the designers, which in turn, seek to adopt new design methods to increase their productivity. As an answer to these new pressures, modern day systems have moved towards on-chip multiprocessing technologies. New architectures have emerged in on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Platform-based design is a possible solution in addressing these challenges. The principle behind the approach is to separate the functionality of an application from the organization and communication architecture of hardware platform at several levels of abstraction. The existing design methodologies pertaining to platform-based design approach don’t provide full automation at every level of the design processes, and sometimes, the co-design of platform-based systems lead to sub-optimal systems. In addition, the design productivity gap in multiprocessor systems remain a key challenge due to existing design methodologies. This thesis addresses the aforementioned challenges and discusses the creation of a development framework for a platform-based system design, in the context of the SegBus platform - a distributed communication architecture. This research aims to provide automated procedures for platform design and application mapping. Structural verification support is also featured thus ensuring correct-by-design platforms. The solution is based on a model-based process. Both the platform and the application are modeled using the Unified Modeling Language. This thesis develops a Domain Specific Language to support platform modeling based on a corresponding UML profile. Object Constraint Language constraints are used to support structurally correct platform construction. An emulator is thus introduced to allow as much as possible accurate performance estimation of the solution, at high abstraction levels. VHDL code is automatically generated, in the form of “snippets” to be employed in the arbiter modules of the platform, as required by the application. The resulting framework is applied in building an actual design solution for an MP3 stereo audio decoder application.

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The augmented reality (AR) technology has applications in many fields as diverse as aeronautics, tourism, medicine, and education. In this review are summarized the current status of AR and it is proposed a new application of it in weed science. The basic algorithmic elements for AR implementation are already available to develop applications in the area of weed economic thresholds. These include algorithms for image recognition to identify and quantify weeds by species and software for herbicide selection based on weed density. Likewise, all hardware necessary for AR implementation in weed science are available at an affordable price for the user. Thus, the authors propose weed science can take a leading role integrating AR systems into weed economic thresholds software, thus, providing better opportunities for science and computer-based weed control decisions.

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Ajoneuvojen reititystä on tutkittu 1950-luvulta asti, alunperin etsiessä polttoainekuljetuksille optimaalisinta reittiä varastolta useille palveluasemille. Siitä lähtien ajoneuvon reititystehtäviä on tutkittu akateemisesti ja niistä on muodostettu kymmeniä erilaisia variaatioita. Tehtävien ratkaisumenetelmät jaetaan tyypillisesti tarkkoihin menetelmiin sekä heuristiikkoihin ja metaheuristiikkoihin. Konetehon ja heuristiikoissa käytettävien algoritmien kehittymisen myötä reitinoptimointia on alettu tarjota kaupallisesti. CO-SKY-projektin tavoitteena on kaupallistaa web-pohjainen tai toiminnanohjausjärjestelmään integroitava ajoneuvon reititys. Diplomityössä tutkitaan kuljetustensuunnittelu- ja reitinoptimointiohjelmistojen kaupallistamiseen vaikuttavia keskeisiä ominaisuuksia. Ominaisuuksia on tarkasteltu: 1) erityisesti pk-kuljetusyritysten tarpeiden ja vaatimusten pohjalta, ja 2) markkinoilla olevien ohjelmistojen tarjontaa arvioiden. Näiden pohjalta on myös pyritty arvioimaan kysynnän ja tarjonnan kohtaamista. Pilottiasiakkaita haastattelemalla ohjelmistolle on kyetty asettamaan vaatimuksia, mutta samalla on kuultu käyttäjien mielipiteitä optimoinnista. Lukuisia logistiikkaohjelmistojen tarjoajia on haastateltu logistiikkamessuilla sekä Suomessa että Saksassa. Haastattelujen perusteella on saatu käsitys kyseisistä ohjelmista sekä optimoinnin tarjonnasta että kysynnästä. Akateeminen tutkimus aiheesta on laajaa, koskien niin teknistä toteutusta kuin myös (kysely-)tutkimuksia tarjolla olevien ohjelmistojen ominaisuuksista ja laadusta. Kuljetusyritysten tarpeissa on vaihtelua yritys- ja alakohtaisesti. Perusongelmat ovat samoja, joita reitinoptimoinnin akateemisessa tutkimuksessa käsitellään ja joita kaupalliset ohjelmistot pystyvät ratkaisemaan. Vaikka reitinoptimoinnilla saatavat hyödyt ovat mitattavissa, suunnittelu etenkin pk-yrityksissä tehdään pääosin yhä käsin. Messuhaastattelujen ja loppukäyttäjien mielipiteiden perusteella voidaan todeta kaupallisten ratkaisujen olevan suunniteltu isommille kuljetusyrityksille: tyypillisen it-projektin hinta, käyttöönottoaika ja asennus sekä ratkaisun takaisinmaksuaika vaikuttavat pk-yritysten hankintapäätökseen. Kaupallistamiseen liittyen haasteet liittyvät erityisesti segmentointiin ja markkinointiin asiakasarvon todentamisen ja sen välittämisen kautta.

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The Laboratory of Intelligent Machine researches and develops energy-efficient power transmissions and automation for mobile construction machines and industrial processes. The laboratory's particular areas of expertise include mechatronic machine design using virtual technologies and simulators and demanding industrial robotics. The laboratory has collaborated extensively with industrial actors and it has participated in significant international research projects, particularly in the field of robotics. For years, dSPACE tools were the lonely hardware which was used in the lab to develop different control algorithms in real-time. dSPACE's hardware systems are in widespread use in the automotive industry and are also employed in drives, aerospace, and industrial automation. But new competitors are developing new sophisticated systems and their features convinced the laboratory to test new products. One of these competitors is National Instrument (NI). In order to get to know the specifications and capabilities of NI tools, an agreement was made to test a NI evolutionary system. This system is used to control a 1-D hydraulic slider. The objective of this research project is to develop a control scheme for the teleoperation of a hydraulically driven manipulator, and to implement a control algorithm between human and machine interaction, and machine and task environment interaction both on NI and dSPACE systems simultaneously and to compare the results.

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Presentation at Open Repositories 2014, Helsinki, Finland, June 9-13, 2014

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We describe a low-cost, high quality device capable of monitoring indirect activity by detecting touch-release events on a conducting surface, i.e., the animal's cage cover. In addition to the detecting sensor itself, the system includes an IBM PC interface for prompt data storage. The hardware/software design, while serving for other purposes, is used to record the circadian activity rhythm pattern of rats with time in an automated computerized fashion using minimal cost computer equipment (IBM PC XT). Once the sensor detects a touch-release action of the rat in the upper portion of the cage, the interface sends a command to the PC which records the time (hours-minutes-seconds) when the activity occurred. As a result, the computer builds up several files (one per detector/sensor) containing a time list of all recorded events. Data can be visualized in terms of actograms, indicating the number of detections per hour, and analyzed by mathematical tools such as Fast Fourier Transform (FFT) or cosinor. In order to demonstrate method validation, an experiment was conducted on 8 Wistar rats under 12/12-h light/dark cycle conditions (lights on at 7:00 a.m.). Results show a biological validation of the method since it detected the presence of circadian activity rhythm patterns in the behavior of the rats

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In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

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Microsoft System Center Configuration Manager is a systems management product for managing large groups of computers and/or mobile devices. It provides operating system deployment, software distribution, patch management, hardware & software inventory, remote control and many other features for the managed clients. This thesis focuses on researching whether this product is suitable for large, international organization with no previous, centralized solution for managing all such networked devices and detecting areas, where the system can be altered to achieve a more optimal management product from the company’s perspective. The results showed that the system is suitable for such organization if properly configured and clear and transparent line of communication between key IT personnel exists.

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TIIVISTELMÄ Tekijä: Urpalainen, Mika Tutkielman nimi: Miten kehittää ketjuliiketoimintaa rautakaupassa Case: Rautanet Tiedekunta: Kauppatieteellinen tiedekunta Pääaine / Maisteriohjelma: Kansainvälinen markkinointi Vuosi: 2014 Pro gradu – tutkielma: Lappeenrannan teknillinen yliopisto, 129 sivua, 28 kuvaa, 15 taulukkoa ja kaksi liitettä Tarkastajat: prof. Olli Kuivalainen, prof. Sanna-Katriina Asikainen Hakusanat: ketjutoiminta, Rautanet-ketju, sitoutuminen, markkinointi Keywords: Chain business, Rautanet-chain, commitment, marketing Rautanet-ketju on heterogeeninen, vapaaehtoisuuteen perustuva rautakauppaketju, joka on perustettu vuonna 1998. Tämän tutkimuksen tarkoituksena on selvittää Rautanet-kauppiaille ja koko ketjuorganisaatiolle ketjutoiminnan etuja, haasteita sekä kauppiaskunnan näkemyksiä ketjutoiminnasta tänä päivänä. Tutkimusmenetelmä oli kvalitatiivinen ja kvantitatiivinen, se perustui kauppiaille lähetettyyn kyselylomakkeeseen, joka sisälsi Likert-asteikollisia kysymyksiä 36 ja 3 kysymystä joihin vastattiin kirjallisesti. Kysymykset sisälsivät aiheita mm. Sitoutumisesta, markkinoinnista, sidosryhmistä jne. Tutkimusjoukkona oli Rautanet-kauppiaat. Kokonaisuutena arvioiden kauppiaat ovat tyytyväisiä ketjun toimintaan. Suurimmat edut ovat markkinointituki kuvastojen avulla ja ketjun voima, jonka kauppiaat tekevät yhdessä. Etuna voidaan pitää myös kauppiaiden sitoutumishalukkuutta ketjuun. Suurimpana haasteena on ehkä itsenäisyyden menettämisen pelko. Rautanet-ketjun toiminta on hyvällä tasolla. Kilpailun kiristyessä myös Rautanet-ketjun kauppiaiden sitoutumishalukkuutta on pidettävä yllä. Ketjuorganisaation on kunnioitettava kauppiaan itsenäisyyttä ja kuunneltava jatkossakin kauppiaita. Ketjun ja kauppiaiden selkeä yhteinen päämäärä, rakentaa vahva ketju, joka pystyy vastaamaan kilpailijoiden haasteisiin, on hyvin paljon riippuvainen yhdessä tekemisen halusta.

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Tässä työssä esiteltiin Android laitteisto- ja sovellusalustana sekä kuvattiin, kuinka Android-pelisovelluksen käyttöliittymä voidaan pitää yhtenäisenä eri näyttölaitteilla skaalauskertoimien ja ankkuroinnin avulla. Toisena osiona työtä käsiteltiin yksinkertaisia tapoja, joilla pelisovelluksien suorituskykyä voidaan parantaa. Näistä tarkempiin mittauksiin valittiin matalatarkkuuksinen piirtopuskuri ja näkymättömissä olevien kappaleiden piilotus. Mittauksissa valitut menetelmät vaikuttivat demosovelluksen suorituskykyyn huomattavasti. Tässä työssä rajauduttiin Android-ohjelmointiin Java-kielellä ilman ulkoisia kirjastoja, jolloin työn tuloksia voi helposti hyödyntää mahdollisimman monessa eri käyttökohteessa.

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This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.