Comparative analysis of static and switching performance of 1.2 kV commercial SiC transistors for high power density applications

This paper presents a critical comparison of static and switching performance of commercially available 1.2 kV SiC BJTs, MOSFETs and JFETs with 1.2 kV Si IGBTs. The experiments conducted are mainly focussed on investigating the temperature dependence of device performance. As an emerging commercial device, special emphasis is placed on SiC BJTs. The experimental data indicate that the SiC BJTs have relatively smaller conduction, off-state and turn-off switching losses, in comparison to the other devices. Furthermore, SiC BJTs have demonstrated much higher static current gain values in comparison to their silicon counterparts, thereby minimising driver losses. Based on the results, the suitability of SiC devices for high power density applications has been discussed. © 2013 IEEE.

Multiple valley couplings in nanometer Si metal-oxide-semiconductor field-effect transistors

We investigate the couplings between different energy band valleys in a metal-oxide-semiconductor field-effect transistor (MOSFET) device using self-consistent calculations of million-atom Schrodinger-Poisson equations. Atomistic empirical pseudopotentials are used to describe the device Hamiltonian and the underlying bulk band structure. The MOSFET device is under nonequilibrium condition with a source-drain bias up to 2 V and a gate potential close to the threshold potential. We find that all the intervalley couplings are small, with the coupling constants less than 3 meV. As a result, the system eigenstates derived from different bulk valleys can be calculated separately. This will significantly reduce the simulation time because the diagonalization of the Hamiltonian matrix scales as the third power of the total number of basis functions. (C) 2008 American Institute of Physics.

Transfer and detection of single electrons using metal-oxide-semiconductor field-effect transistors

A single-electron turnstile and electrometer circuit was fabricated on a silicon-on-insulator substrate. The turnstile, which is operated by opening and closing two metal-oxide-semiconductor field-effect transistors (MOSFETs) alternately, allows current quantization at 20 K due to single-electron transfer. Another MOSFET is placed at the drain side of the turnstile to form an electron storage island. Therefore, one-by-one electron entrance into the storage island from the turnstile can be detected as an abrupt change in the current of the electrometer, which is placed near the storage island and electrically coupled to it. The correspondence between the quantized current and the single-electron counting was confirmed.

Quantum mechanical effects in nanometer field effect transistors

The atomistic pseudopotential quantum mechanical calculations for million atom nanosized metal-oxide-semiconductor field-effect transistors (MOSFETs) are presented. When compared with semiclassical Thomas-Fermi simulation results, there are significant differences in I-V curve, electron threshold voltage, and gate capacitance. In many aspects, the quantum mechanical effects exacerbate the problems encountered during device minimization, and it also presents different mechanisms in controlling the behaviors of a nanometer device than the classical one. (c) 2007 American Institute of Physics.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Fabrication of improved FD SOIMOSFETs for suppressing edge effect

FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to reduce the edge effect and qualified devices are fabricated successfully.

THE DEPENDENCE OF THE INVERSION LAYER THICKNESS ON THE FILM THICKNESS IN THIN-FILM SOI STRUCTURES

The dependence of the inversion-layer thickness on the film thickness in thin-film SOI structure is analyzed theoretically by using computer simulation. A new concept and parameter, the critical thickness of thin film all-bulk inversion, is introduced for the design of thin-film MOS/SOI devices. It is necessary to select the film thickness T(s1) close to the all-bulk strong inversion critical thickness in order to get high-speed and high-power operation of ultra-thin film MOS/SOI devices.

一种性能优良稳定的微功耗CMOS电压积分器

本文提出了一种电源波动影响弱、低温飘、微功耗（〈1μw）的CMOS电压型积分器电路。它利用自偏置的恒流源电路结构以及MOSFETs的亚阈值特性产生一个nA级的恒流源，通过控制电路实现对电容充放电来获得积分电压。并且对电路结构、器件类型和器件尺寸进行了优化。仿真结果表明，得到了独立于电源电压、低温度系数、微功耗的积分电压。

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Junctionless 6T SRAM cell

.The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 mA along with a low leakage current of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pullup ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Optimisation and scaling of interfacial GeO2 layers for high-k gate stacks on germanium and extraction of dielectric constant of GeO2

Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon. In this paper, GeO2 has been investigated as an interfacial layer for high-kappa gate stacks on germanium. Thermally grown GeO2 layers have been prepared at 550 degrees C to minimise GeO volatilisation. GeO2 growth has been performed in both pure O-2 ambient and O-2 diluted with N-2. GeO2 thickness has been scaled down to approximately 3 nm. MOS capacitors have been fabricated using different GeO2 thicknesses with a standard high-kappa dielectric on top. Electrical properties and thermal stability have been tested up to at least 350 degrees C. The K value of GeO2 was experimentally determined to be 4.5. Interface state densities (D-it) of less than 10(12) CM-2 eV(-1) have been extracted for all devices using the conductance method.

New SR drive with integrated charging capacity for plug-in hybrid electric vehicles (PHEVs)

Plug-in hybrid electric vehicles (PHEVs) provide much promise in reducing greenhouse gas emissions and, thus, are a focal point of research and development. Existing on-board charging capacity is effective but requires the use of several power conversion devices and power converters, which reduce reliability and cost efficiency. This paper presents a novel three-phase switched reluctance (SR) motor drive with integrated charging functions (including internal combustion engine and grid charging). The electrical energy flow within the drivetrain is controlled by a power electronic converter with less power switching devices and magnetic devices. It allows the desired energy conversion between the engine generator, the battery, and the SR motor under different operation modes. Battery-charging techniques are developed to operate under both motor-driving mode and standstill-charging mode. During the magnetization mode, the machine's phase windings are energized by the dc-link voltage. The power converter and the machine phase windings are controlled with a three-phase relay to enable the use of the ac-dc rectifier. The power converter can work as a buck-boost-type or a buck-type dc-dc converter for charging the battery. Simulation results in MATLAB/Simulink and experiments on a 3-kW SR motor validate the effectiveness of the proposed technologies, which may have significant economic implications and improve the PHEVs' market acceptance