Universal power quality manager with a new control scheme

A new universal power quality manager is proposed. The proposal treats a number of power quality problems simultaneously. The universal manager comprises a combined series and shunt three-phase PWM controlled converters sharing a common DC link. A control scheme based on fuzzy logic is introduced and the general features of the design and operation processes are outlined. The performance of two configurations of the proposed power quality manager are compared in terms of a recently formulated unified power quality index. The validity and integrity of the proposed system is proved through computer simulated experiments

Plasma power measurement and hysteresis in the E-H transition of a rf inductively coupled plasma system

An experimental investigation of the argon plasma behavior near the E-H transition in an inductively coupled Gaseous Electronics Conference reference cell is reported. Electron density and temperature, ion density, argon metastable density, and optical emission measurements have been made as function of input power and gas pressure. When plotted versus plasma power, applied power corrected for coil and hardware losses, no hysteresis is observed in the measured plasma parameter dependence at the E-H mode transition. This suggests that hysteresis in the E-H mode transition is due to ignoring inherent power loss, primarily in the matching system.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

The control of wave energy converters using active bipolar damping

A novel method for controlling wave energy converters using active bipolar damping is described and compared with current control methods. The performance of active bipolar damping is modelled numerically for two distinct types of wave energy converter and it is found that in both cases the power capture can be significantly increased relative to optimal linear damping. It is shown that this is because active bipolar damping has the potential for providing a quasi-spring or quasi-inertia, which improves the wave energy converter's tuning and amplitude of motion, resulting in the increase in power capture observed. The practical implementation of active bipolar damping is also discussed. It is noted that active bipolar damping does not require a reactive energy store and thereby reduces the cost and eliminates losses due to the cycling of reactive energy. It is also noted that active bipolar damping could be implemented using a single constant pressure double-acting hydraulic cylinder and so potentially represents a simple, efficient, robust and economic solution to the control of wave energy converters.

Envelope-tracking-based Doherty power amplifier

From the instantaneous efficiency plot, it is observed that the conventional 2-stage Doherty power amplifier (DPA) with high upper power dynamic range (>12 dB) suffers from a substantial dip in the middle of the upper power regime, thus reducing the average efficiency. In this study, an envelope-tracking-based DPA is proposed in order to minimise this dip by adjusting the drain bias voltage of the auxiliary amplifier of the DPA proportional to the input power level.

Randomized caches for power-efficiency

Embedded processors are used in numerous devices executing dedicated applications. This setting makes it worthwhile to optimize the processor to the application it executes, in order to increase its power-efficiency. This paper proposes to enhance direct mapped data caches with automatically tuned randomized set index functions to achieve that goal. We show how randomization functions can be automatically generated and compare them to traditional set-associative caches in terms of performance and energy consumption. A 16 kB randomized direct mapped cache consumes 22% less energy than a 2-way set-associative cache, while it is less than 3% slower. When the randomization function is made configurable (i.e., it can be adapted to the program), the additional reduction of conflicts outweighs the added complexity of the hardware, provided there is a sufficient amount of conflict misses.

2.4 GHz high-efficiency power-combining Class-E amplifier with transmission-line harmonic traps

Experimental assessments of the modified power-combining Class-E amplifier are described. The technique used to combine the output of individual power amplifiers (PAs) into an unbalanced load without the need for bulky transformers permits the use of small RF chokes useful for the deployment in the EER transmitter. The modified output load network of the PA results in excellent 50 dBc and 46 dBc second and third-harmonic suppressions, dispensing the need for additional lossy filtering block. Operating from a 3.2 V dc supply voltage, the PA exhibits 64% drain efficiency at 24 dBm output power. Over a wide bandwidth of 350 MHz, drain efficiency of better than 60% at output power higher than 22 dBm were achieved. © 2010 IEICE Institute of Electronics Informati.

Design technique for mm-wave IC realization of the load network of switched-mode class-EF power amplifier

Analysis and synthesis of the new Class-EF power amplifier (PA) are presented in this paper. The proposed circuit offers means to alleviate some of the major issues faced by existing Class-EF and Class-EF PAs, such as (1) substantial power losses due to parasitic resistance of the large inductor in the Class-EF load network, (2) unpredictable behaviour of practical lumped inductors and capacitors at harmonic frequencies, and (3) deviation from ideal Class-EF operation mode due to detrimental effects of device output inductance at high frequencies. The transmission-line load network of the Class-EF PA topology elaborated in this paper simultaneously satisfies the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Furthermore, an elegant solution using an open and short-circuit stub arrangement is suggested to overcome the problem encountered in the mm-wave IC realizations of the Class-EF PA load network due to lossy quarter-wave line. © 2010 IEICE Institute of Electronics Informati.