Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Fabrication and characterization of metal-semiconductor-metal (MSM) ultraviolet photodetectors on undoped GaN/sapphire grown by MBE

Interdigital metal-semiconductor-metal (MSM) ultraviolet photoconductive detectors have been fabricated on undoped GaN films grown by molecular beam epitaxy (MBE), Response dependence on wavelength, applied current, excitation powers and chopper frequency has been extensively investigated. It is shown that the photodetector's spectral response remained nearly constant for wavelengths above the band gap and dropped sharply by almost three orders of magnitude for wavelengths longer than the band gap. It increases linearly with the applied constant current, but very nonlinearly with illuminating power. The photodetectors showed high photoconductor gains resulting from trapping of minority carriers (holes) at acceptor impurities or defects. The results demonstrated the high quality of the GaN crystal used to fabricate these devices. (C) 2000 Elsevier Science B.V. All rights reserved.

Si1-xGex/Si resonant-cavity-enhanced photodetectors with a silicon-on-oxide reflector operating near 1.3 mu m

We report on a Si1-xGex/Si multiple quantum-well resonant-cavity-enhanced (RCE) photodetector with a silicon-on-oxide reflector as the bottom mirror operating near 1.3 mu m. The breakdown voltage of the photodetector is above 18 V and the dark current density at 5 V reverse bias is 12 pA/mu m(2). The RCE photodetector shows enhanced responsivity with a clear peak at 1.285 mu m and the peak responsivity is measured around 10.2 mA/W at a reverse bias of 5 V. The external quantum efficiency at 1.3 mu m is measured to be 3.5% under reverse bias of 16 V, which is enhanced three- to fourfold compared with that of a conventional p-i-n photodetector with a Ge content of 0.5 reported in 1995 by Huang [Appl. Phys. Lett. 67, 566 (1995)]. (C) 2000 American Institute of Physics. [S0003-6951(00)00628-8].

Design considerations for a silicon-based p-i-n phase modulator in a double ridge waveguide with side isolating grooves

We present detail design considerations and simulation results of a forward biased carrier injection p-i-n modulator integrated on SOI rib waveguides. To minimize the free carrier absorption loss while keeping the comparatively small lateral dimensions of the modulator as required for high speed operation, we proposed two structural improvements, namely the double ridge (terrace ridge) structure and the isolating grooves at both sides of the double ridge. With improved carrier injection and optical confinement structure, the simulated modulator response time is in sub-ns range and absorption loss is minimized.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

SHicon-based resonant-cavity-enhanced photodetectors

Silicon-based resonant-cavity-enhanced photodetectors (RCE-PD) with Si, Ge islands and InGaAs as absorption materials were introduced, respectively. The Ge islands and Si RCE-PD had a membrane structure and the Si-based InGaAs RCE-PDs were fabricated by bonding technology.

An ambient proof and wide tuning range LC VCO with automatic amplitude control for tuner applications

This paper represents a LC VCO with AAC (Auto Amplitude Control), in which PMOS FETs are used as active components, and the varactors are directly connected to ground to widen Kvco linear range. The AAC circuitry adds little noise to the VCO and provides it with robust performance over a wide temperature and carrier frequency range. The VCO is fabricated in 50-GHz 0.35-mu m SiGe BiCMOS process. The measurement results show that it has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole circuit draws 6.6-mA current from 5.0-V supply.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

A Novel CMOS Color Pixel for Vision Chips

This paper presents a novel CMOS color pixel with a 2D metal-grating structure for real-time vision chips. It consists of an N-well/P-substrate diode without salicide and 2D metal-grating layers on the diode. The periods of the 2D metal structure are controlled to realize color filtering. We implemented sixteen kinds of the pixels with the different metal-grating structures in a standard 0.18 mu m CMOS process. The measured results demonstrate that the N-well/P-substrate diode without salicide and with the 2D metal-grating structures can serve as the high speed RGB color active pixel sensor for real-time vision chips well.

Design and Characterization of Evanescently Coupled Uni-Traveling Carrier Photodiodes with a Multimode Diluted Waveguide Structure

A new evanescently coupled uni-traveling carrier photodiode (EC-UTC-PD) is designed, fabricated and characterized, which incorporates a multimode diluted waveguide structure and UTC active waveguide structure together. A high responsivity of 0.68A/W at 1.55-mu m without an anti-reflection coating, a linear photocurrent responsivity of more than 21 mA, and a large-1 dB vertical alignment tolerance of 2.5 mu m are achieved.

A 10 Gb/s Directly-Modulated 1.3 mu m InAs/GaAs Quantum-Dot Laser

We demonstrate 10 Gb/s directly-modulated 1.3 mu m InAs quantum-dot (QD) lasers grown on GaAs substrates by molecular beam epitaxy. The active region of the QD lasers consists of five-stacked InAs QD layers. Ridge-waveguide lasers with a ridge width of 4 mu m and a cavity length of 600 mu m are fabricated with standard lithography and wet etching techniques. It is found that the lasers emit at 1293 nm with a very low threshold current of 5 mA at room temperature. Furthermore, clear eye-opening patterns under 10 Gb/s modulation rate at temperatures of up to 50 degrees C are achieved by the QD lasers. The results presented here have important implications for realizing low-cost, low-power-consumption, and high-speed light sources for next-generation communication systems.

Uniform mems chip temperatures in the nucleate boiling heat transfer region by selecting suitable, medium boiling number range

The not only lower but also uniform MEMS chip temperatures can he reached by selecting suitable boiling number range that ensures the nucleate boiling heat transfer. In this article, boiling heat transfer experiments in 10 silicon triangular microchannels with the hydraulic diameter of 55.4 mu m were performed using acetone as the working fluid, having the inlet liquid temperatures of 24-40 degrees C, mass fluxes of 96-360 kg/m(2)s, heat fluxes of 140-420 kW/m(2), and exit vapor mass qualities of 0.28-0.70. The above data range correspond to the boiling number from 1.574 x 10(-3) to 3.219 x 10(-3) and ensure the perfect nucleate boiling heat transfer region, providing a very uniform chip temperature distribution in both streamline and transverse directions. The boiling heat transfer coefficients determined by the infrared radiator image system were found to he dependent on the heat Axes only, not dependent on the mass Axes and the vapor mass qualities covering the above data range. The high-speed flow visualization shows that the periodic flow patterns take place inside the microchannel in the time scale of milliseconds, consisting of liquid refilling stage, bubble nucleation, growth and coalescence stage, and transient liquid film evaporation stage in a full cycle. The paired or triplet bubble nucleation sites can occur in the microchannel corners anywhere along the flow direction, accounting for the nucleate boiling heat transfer mode. The periodic boiling process is similar to a series of bubble nucleation, growth, and departure followed by the liquid refilling in a single cavity for the pool boiling situation. The chip temperature difference across the whole two-phase area is found to he small in a couple of degrees, providing a better thermal management scheme for the high heat flux electronic components. Chen's [11 widely accepted correlation for macrochannels and Bao et al.'s [21 correlation obtained in a copper capillary tube with the inside diameter of 1.95 mm using R11 and HCFC123 as working fluids can predict the present experimental data with accepted accuracy. Other correlations fail to predict the correct heat transfer coefficient trends. New heat transfer correlations are also recommended.

Pool boiling heat transfer of ultra-light copper foam with open cells

High speed visualizations and thermal performance studies of pool boiling heat transfer on copper foam covers were performed at atmospheric pressure, with the heating surface area of 12.0 mm by 12.0 mm, using acetone as the working fluid. The foam covers have ppi (pores per inch) from 30 to 90, cover thickness from 2.0 to 5.0 mm, and porosity of 0.88 and 0.95. The surface superheats are from -20 to 190 K, and the heat fluxes reach 140 W/cm(2). The 30 and 60 ppi foam covers show the periodic single bubble generation and departure pattern at low surface superheats. With continuous increases in surface superheats, they show the periodic bubble coalescence and/or re-coalescence pattern. Cage bubbles were observed to be those with liquid filled inside and vented to the pool liquid. For the 90 ppi foam covers, the bubble coalescence takes place at low surface superheats. At moderate or large surface superheats, vapor fragments continuously escape to the pool liquid. Boiling curves of copper foams show three distinct regions. Region I and II are those of natural convection heat transfer, and nucleate boiling heat transfer for all the foam covers. Region III is that of either a resistance to vapor release for the 30 and 60 ppi foam covers, or a capillary-assist liquid flow towards foam cells for the 90 ppi foam covers. The value of ppi has an important effect on the thermal performance. Boiling curves are crossed between the high and low ppi foam covers. Low ppi foams have better thermal performance at low surface superheats, but high ppi foams have better one at moderate or large surface superheats and extend the operation range of surface superheats. The effects of other factors such as pool liquid temperature, foam cover thickness on the thermal performance are also discussed.