993 resultados para Standard architecture


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Reported mast-cell counts in endobronchial biopsies from asthmatic subjects are conflicting, with different methodologies often being used. This study compared three standard methods of counting mast cells in endobronchial biopsies from asthmatic and normal subjects. Endobronchial biopsies were obtained from atopic asthmatic subjects (n=17), atopic nonasthmatic subjects (n=6), and nonatopic nonasthmatic control subjects (n=5). After overnight fixation in Carnoy's fixative, mast cells were stained by the short and long toluidine blue methods and antitryptase immunohistochemistry and were counted by light microscopy. Method comparison was made according to Bland & Altman. The limits of agreement were unacceptable for each of the comparisons, suggesting that the methods are not interchangeable. Coefficients of repeatability were excellent, and not different for the individual techniques. These results suggest that some of the reported differences in mast-cell numbers in endobronchial biopsies in asthma may be due to the staining method used, making direct comparisons between studies invalid. Agreement on a standard method is required for counting mast cells in bronchial biopsies, and we recommend the immunohistochemical method, since fixation is less critical and the resultant tissue sections facilitate clear, accurate, and rapid counts.

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An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

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A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

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A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

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In this paper, a new reconfigurable multi-standard Motion Estimation (ME) architecture is proposed and a standard-cell based design study is presented. The architecture exhibits simpler control, high throughput and relative low hardware cost and is highly competitive when compared with existing designs for specific video standards. ©2007 IEEE.