A Virtex FPGA Implementation of Matrix Product Based on 2-D Bit-Level Systolic Architecture

Autoria(s): Amira, Abbes; Bouridane, Ahmed; Milligan, Peter; Nibouche, M.
Data(s)

01/11/2000
Identificador

http://pure.qub.ac.uk/portal/en/publications/a-virtex-fpga-implementation-of-matrix-product-based-on-2d-bitlevel-systolic-architecture(d7fc5256-a0ce-4007-ba28-bd24a4cc7bf7).html
Idioma(s)

eng
Direitos

info:eu-repo/semantics/restrictedAccess
Fonte

Amira , A , Bouridane , A , Milligan , P & Nibouche , M 2000 , ' A Virtex FPGA Implementation of Matrix Product Based on 2-D Bit-Level Systolic Architecture ' Paper presented at 1st International Conference on Electronic Engineering , Bourmedes , Algeria , 01/11/2000 - 01/11/2000 , pp. 1-8 .
Tipo

conferenceObject
Acesso ao item digital