IMPLEMENTATION OF SIGNAL PROCESSING FUNCTIONS USING 1-BIT SYSTOLIC ARRAYS.

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

UTILISATION OF BIT LEVEL SYSTOLIC ARRAYS IN WORD LEVEL SYSTEMS.

Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.

MAPPING SYSTEM LEVEL FUNCTIONS ON TO BIT LEVEL SYSTOLIC ARRAYS.

Bit-level systolic-array structures for computing sums of products are studied in detail. It is shown that these can be subdivided into two classes and that within each class architectures can be described in terms of a set of constraint equations. It is further demonstrated that high-performance system-level functions with attractive VLSI properties can be constructed by matching data-flow geometries in bit-level and word-level architectures.

BIT-LEVEL SYSTOLIC ARRAYS.

A systolic array is an array of individual processing cells each of which has some local memory and is connected only to its nearest neighbours in the form of a regular lattice. On each cycle of a simple clock every cell receives data from its neighbouring cells and performs a specific processing operation on it. The resulting data is stored within the cell and passed on to neighbouring cells on the next clock cycle. This paper gives an overview of work to date and illustrates the application of bit-level systolic arrays by means of two examples: (1) a pipelined bit-slice circuit for computing matrix x vector transforms; and (2) a bit serial structure for multi-bit convolution.

RELATIONSHIP BETWEEN WORD AND BIT LEVEL SYSTOLIC ARRAYS AS APPLIED TO MATRIX multiplied by MATRIX MULTIPLICATIONS.

The mapping of matrix multiplied by matrix multiplication onto both word and bit level systolic arrays has been investigated. It has been found that well defined word and bit level data flow constraints must be satisfied within such circuits. An efficient and highly regular bit level array has been generated by exploiting the basic compatibilities in data flow symmetries at each level of the problem. A description of the circuit which emerges is given and some details relating to its practical implementation are discussed.

Use of data dependence graphs in the design of bit-level systolic arrays

The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S. Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.

VQ tree search system based on bit level systolic arrays

A bit-level systolic array system for performing a binary tree vector quantization (VQ) codebook search is described. This is based on a highly regular VLSI building block circuit. The system in question exhibits a very high data rate suitable for a range of real-time applications. A technique is described which reduces the storage requirements of such a system by 50%, with a corresponding decrease in hardware complexity.

BIT-LEVEL SYSTOLIC ARRAYS FOR SIGNAL AND IMAGE PROCESSING.

This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of image processing operations where high performance and throughput are essential. The architecture is illustrated by describing the operation of the correlator and convolver chips which are being developed. The advantage of the system is also discussed.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

Dual-Reflector Antenna with a Reflectarray Subreflector for Wide Beam Scanning Range at 120GHz

A dual-reflector antenna composed by a small reconfigurable reflectarray subreflector and a large parabolic main reflector is proposed for beam scanning application in the 120 GHz frequency band. The beam scanning is achieved by changing the phase distribution on the reflectarray surface which is supposed to contain reconfigurable cells. The phase distribution for the different beam deflecting states is obtained with a synthesis technique based on the analysis of the antenna in receive mode.

W-Band Planar Wide-Angle Scanning Antenna Architecture

This paper proposes a hybrid scanning antenna architecture for applications in mm-wave intelligent mobile sensing and communications. We experimentally demonstrate suitable W-band leaky-wave antenna prototypes in substrate integrated waveguide (SIW) technology. Three SIW antennas have been designed that within a 6.5 % fractional bandwidth provide beam scanning over three adjacent angular sectors. Prototypes have been fabricated and their performance has been experimentally evaluated. The measured radiation patterns have shown three frequency scanning beams covering angles from 11 to 56 degrees with beamwidth of 10?±?3 degrees within the 88-94 GHz frequency range.

Influence of skin model on in vitro performance of drug-loaded soluble microneedle arrays

A plethora of studies have described the in vitro assessment of dissolving microneedle (MN) arrays for enhanced transdermal drug delivery, utilising a wide variety of model membranes as a representation of the skin barrier. However, to date, no discussion has taken place with regard to the choice of model skin membrane and the impact this may have on the evaluation of MN performance. In this study, we have, for the first time, critically assessed the most common types of in vitro skin permeation models - a synthetic hydrophobic membrane (Silescol(®) of 75 µm) and neonatal porcine skin of definable thickness (300-350 µm and 700-750 µm) - for evaluating the performance of drug loaded dissolving poly (methyl vinyl ether co maleic acid) (PMVE/MA) MN arrays. It was found that the choice of in vitro skin model had a significant effect on the permeation of a wide range of small hydrophilic molecules released from dissolving MNs. For example, when Silescol(®) was used as the model membrane, the cumulative percentage permeation of methylene blue 24h after the application of dissolvable MNs was found to be only approximately 3.7% of the total methylene blue loaded into the MN device. In comparison, when dermatomed and full thickness neonatal porcine skin were used as a skin model, approximately 67.4% and 47.5% of methylene blue loaded into the MN device was delivered across the skin 24h after the application of MN arrays, respectively. The application of methylene blue loaded MN arrays in a rat model in vivo revealed that the extent of MN-mediated percutaneous delivery achieved was most similar to that predicted from the in vitro investigations employing dermatomed neonatal porcine skin (300-350 µm) as the model skin membrane. On the basis of these results, a wider discussion within the MN community will be necessary to standardise the experimental protocols used for the evaluation and comparison of MN devices.

Design, optimization and characterisation of polymeric microneedle arrays prepared by a novel laser-based micromoulding technique

Design and evaluation of a novel laser-based method for micromoulding of microneedle arrays from polymeric materials under ambient conditions. The aim of this study was to optimise polymeric composition and assess the performance of microneedle devices that possess different geometries.