Effect of inter-level relaxation and cavity length on double-state lasing performance of quantum dot lasers

Double-state lasing phenomena are easily observed in self-assembled quantum dot (QD) lasers. The effect of inter-level relaxation rate and cavity length on the double-state lasing performance of QD lasers is investigated on the basis of a rate equation model. Calculated results show that, for a certain cavity length, the ground state (GS) lasing threshold current increases almost linearly with the inter-level relaxation lifetime. However, as the relaxation rate becomes slower, the ratio of excited state (ES) lasing threshold current over the GS one decreases, showing an evident exponential behavior. A relatively feasible method to estimate the inter-level relaxation lifetime, which is difficult to measure directly, is provided. In addition, fast inter-level relaxation is favorable for the GS single-mode lasing, and leads to lower wetting layer (WL) carrier occupation probability and higher QD GS capture efficiency and external differential quantum efficiency. Besides, the double-state lasing effect strongly depends on the cavity length. (c) 2007 Elsevier B.V. All rights reserved.

Application of ICA in on-line verification of the phase difference of the current sensor

The performance of the current sensor in power equipment may become worse affected by the environment. In this paper, based on ICA, we propose a method for on-line verification of the phase difference of the current sensor. However, not all source components are mutually independent in our application. In order to get an exact result, we have proposed a relative likelihood index to choose an optimal result from different runs. The index is based on the maximum likelihood evaluation theory and the independent subspace analysis. The feasibility of our method has been confirmed by experimental results.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Spin-polarized current produced by a double barrier resonant tunneling diode

The spin-polarized tunneling current through a double barrier resonant tunneling diode (RTD) made with a semimagnetic semiconductor is studied theoretically. The calculated spin-polarized current and polarization degree are in agreement with recent experimental results. It is predicted that the polarization degree can be modulated continuously from + 1 to - 1 by changing the external voltage such that the quasi-confined spin-up and spin-down energy levels shift downwards from the Fermi level to the bottom of the conduction band. The RTD with low potential barrier or the tunneling through the second quasi-confined state produces larger spin-polarized current. Furthermore a higher magnetic field enhances the polarization degree of the tunneling current. (C) 2003 Elsevier Ltd. All rights reserved.

Room-temperature, ground-state lasing for red-emitting vertically aligned InAlAs/AlGaAs quantum dots grown on a GaAs(100) substrate

The effect of the growth temperature on the properties of InAlAs/AlGaAs quantum dots grown on GaAs(100) substrates is investigated. The optical efficiency and structural uniformity are improved by increasing the growth temperature from 530 to 560 degreesC. The improvements of InAlAs/AlGaAs quantum-dot characteristics could be explained by suppressing the incorporation of oxygen and the formation of group-III vacancies. Furthermore, edge-emitting laser diodes with six quantum-dot layers grown at 560 degreesC have been fabricated. Lasing occurs via the ground state at 725 nm, with a room-temperature threshold current density of 3.9 kA/cm(2), significantly better than previously reported values for this quantum-dot systems. (C) 2002 American Institute of Physics.

Negative differential resistance and the transition to current self-oscillation in GaAs/AlAs superlattices

We investigate the transition from static to dynamic electric field domains (EFDs) in a doped GaAs/AlAs superlattice (SL). We show that a transverse magnetic field and/or the temperature can induce current self-oscillations. This observation can be attributed to the negative differential resistance (NDR) effect. Transverse magnetic field and the temperature can increase the NDR of a doped SL. A large NDR can lead to an unstable EFD in a certain range of d.c. bias. (C) 1999 Elsevier Science Ltd. All rights reserved.

Realization of SOI submicrometer optical waveguide components - art. no. 68380L

Submicrometer channel and rib waveguides based on SOI (Silicon-On-Insulator) have been designed and fabricated with electron-beam lithography and inductively coupled plasma dry etching. Propagation loss of 8.39dB/mm was measured using the cut-back method. Based on these so-called nanowire waveguides, we have also demonstrated some functional components with small dimensions, including sharp 90 degrees bends with radius of a few micrometers, T-branches, directional couplers and multimode interferometer couplers.

High speed silicon optical switches based on carrier depletion - art. no. 67812D

The novel design of a silicon optical switch on the mechanism of a reverse p-n junction is proposed. The figuration of contact regions at slab waveguides and the ion implantation technology for creation of junctions are employed in the new design. The two-layer rib structure is helpful for reduction of optical absorption losses induced by metal and heavily-doped contact. And more, simulation results show that the index modulation efficiency of Mach-Zehnder interferometer enhances as the concentrations of dopants in junctions increase, while the trade-off of absorption loss is less than 3 dB/mu m. The phase shift reaches about 5 x 10(-4) pi/mu m at a reverse bias of 10V with the response time of about 0.2ns. The preliminary experimental results are presented. The frequency bandwidth of modulation operation can arrive in the range of GHz. However, heavily-doped contacts have an important effect on pulse response of these switches. While the contact region is not heavily-doped, that means metal electrodes have schottky contacts with p-n junctions, the operation bandwidth of the switch is limited to about 1GHz. For faster response, the heavily-doped contacts must be considered in the design.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

Application of ICA in on-line verification of the phase difference of the current sensor

The performance of the current sensor in power equipment may become worse affected by the environment. In this paper, based on ICA, we propose a method for on-line verification of the phase difference of the current sensor. However, not all source components are mutually independent in our application. In order to get an exact result, we have proposed a relative likelihood index to choose an optimal result from different runs. The index is based on the maximum likelihood evaluation theory and the independent subspace analysis. The feasibility of our method has been confirmed by experimental results.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Homoepitaxial growth and MOS structures of 4H-SiC on off oriented n-type (0001)Si-faces

Homoepitaxial growth of 4H-SiC on off-oriented n-type Si-face (0001) substrates was performed in a home-made hot-wall low pressure chemical vapor deposition (LPCVD) reactor with SiH4 and C2H4 at temperature of 1500 C and pressure of 20 Torr. The surface morphology and intentional in-situ NH3 doping in 4H-SiC epilayers were investigated by using atomic force microscopy (AFM) and secondary ion mass spectroscopy (SIMS). Thermal oxidization of 4H-SiC homoepitaxial layers was conducted in a dry O-2 and H-2 atmosphere at temperature of 1150 C. The oxide was investigated by employing x-ray photoelectron spectroscopy (XPS). 4H-SiC MOS structures were obtained and their C-V characteristics were presented.