Creation and suppression of point defects through a kick-out substitution process of Fe in InP

Indium antisite defect In-P-related photoluminescence has been observed in Fe-diffused semi-insulating (SI) InP. Compared to annealed undoped or Fe-predoped SI InP, there are fewer defects in SI InP obtained by long-duration, high-temperature Fe diffusion. The suppression of the formation of point defects in Fe-diffused SI InP can be explained in terms of the complete occupation by Fe at indium vacancy. The In-P defect is enhanced by the indium interstitial that is caused by the kick out of In and the substitution at the indium site of Fe in the diffusion process. Through these Fe-diffusion results, the nature of the defects in annealed undoped SI InP is better understood. (C) 2002 American Institute of Physics.

Very low-pressure VLP-CVD growth of high quality gamma-Al2O3 films on silicon by multi-step process

gamma-Al2O3 films were grown on Si (10 0) substrates using the sources of TMA (AI(CH3)(3)) and O-2 by very low-pressure chemical vapor deposition. The effects of temperature control on the crystalline quality, surface morphology, uniformity and dielectricity were investigated. It has been found that the,gamma-Al2O3 film prepared at a temperature of 1000degreesC has a good crystalline quality, but the surface morphology, uniformity and dielectricity were poor due to the etching reaction between 0, and Si substrate in the initial growth stage. However, under a temperature-varied multi-step process the properties Of gamma-Al2O3 film were improved. The films have a mirror-like surface and the dielectricity was superior to that grown under a single-step process. The uniformity of gamma-Al2O3 films for 2-in epi-wafer was <5%, it is better than that disclosed elsewhere. In order to improve the crystalline quality, the gamma-Al2O3 films were annealed for I h in O-2 atmosphere. (C) 2002 Elsevier Science B.V. All rights reserved.

Influences of initial nitridation process on the optical and structural characterization of GaN layer grown on sapphire (0001) by metalorganic chemical vapor deposition

In this paper. we investigate the influences of the initial nitridation of sapphire substrates on the optical and structural characterizations in GaN films. Two GaN samples with and without 3 min nitridation process were investigated by photoluminescence (PL) spectroscopy in the temperature range of 12-300 K and double-crystal X-ray diffraction (XRD). In the 12 K PL spectra of the GaN sample without nitridation, four dominant peaks at 3.476, 3.409 3.362 and 3.308 eV were observed, which were assigned to donor bound exciton, excitons bound to stacking faults and extended structural defects. In the sample with nitridation, three peaks at 3.453, 3.365. and 3.308 eV were observed at 12 K, no peak related to stacking faults. XRD results at different reflections showed that there are more stacking faults in the samples without nitridation.

Carbonization process of Si(100) by ion-beam bombardment

The evolution of carbonization process on Si as a function of ion dose has been carried out by mass-selected ion-beam deposition technique. 3C-SiC layer has been obtained at low ion dose, which has been observed by reflection high energy electron diffraction and X-ray photoelectron spectroscopy (XPS). The chemical states of Si and carbon have also been examined as a function of ion dose by XPS. Carbon enrichment was found regardless of the used ion dose here, which may be due to the high deposition rate. The formation mechanism of SiC has also been discussed based on the subplantation process. The work will also provide further understanding of the ion-bombardment effect. (C) 2001 Published by Elsevier Science B.V.

Growing process of CdS nanoclusters in zeolite Y studied by positron annihilation

Zeolite Y has been used as the host to generate CdS nanoclusters. The location of CdS nanoclusters inside zeolite hosts was confirmed by the blue-shifted reflection absorption spectra with respect to that of bulk CdS materials. But which kind of cage inside zeolite Y, sodalite cage or supercage, was preferred for the CdS clusters remained unclear. In this paper, we conducted positron annihilation spectroscopy (PAS) measurements for the first time on a series of CdS/Y zeolite samples and concluded that CdS clusters were not located in supercages but in smaller sodalite cages. The stability of CdS clusters inside the sodalite units was due to the coordination of Cd atoms with the framework oxygen atoms of the double six-ring windows. Moreover, PAS revealed some important information of surface states existing on the interfacial layers between CdS clusters and zeolite Y. (C) 2001 Elsevier Science B,V, All rights reserved.

Modeling and optimization of semiconductor manufacturing process with neural networks

A neural network-based process model is proposed to optimize the semiconductor manufacturing process. Being different from some works in several research groups which developed neural network-based models to predict process quality with a set of process variables of only single manufacturing step, we applied this model to wafer fabrication parameters control and wafer lot yield optimization. The original data are collected from a wafer fabrication line, including technological parameters and wafer test results. The wafer lot yield is taken as the optimization target. Learning from historical technological records and wafer test results, the model can predict the wafer yield. To eliminate the "bad" or noisy samples from the sample set, an experimental method was used to determine the number of hidden units so that both good learning ability and prediction capability can be obtained.

Biosensors for fermentation process control

Two biosensors for fermentation process control have been introduced, which were developed in our lab recently. One is an enzyme electrode-based on-line monitoring system for glutamate fermentation process control and the other is an H+-ISFET-based ENFET for penicillin G fermentation process control.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

The improvement of thick oxidized porous silicon layer growth process - art. no. 60290S

Oxidizing thick porous silicon layer into silicon dioxide is a timesaving and low-cost process for producing thick silicon dioxide layer used in silicon-based optical waveguide devices. The solution of H2O2 is proposed to post-treat thick porous silicon (PS) films. The prepared PS layer as the cathode is applied about 10 mA/cm(2) current in mixture of ethanol, HF, and H2O2 solutions, in order to improve the stability and the smoothness of the surface. With the low-temperature dry-O-2 pre-oxidizations and high-temperature wet O-2 oxidizations process, a high-quality SiO2 30 mu m thickness layer that fit for the optical waveguide device was prepared. The SEM images show significant improved smoothness on the surface of oxidized PS thick films, the SiO2 film has a stable and uniformity reflex index that measured by the prism coupler, the uniformity of the reflex index in different place of the wafer is about 0.0003.

Preparation and AFM characterization of self-ordered porous alumina films on semi-insulated gaas substrate

Self-ordered porous alumina films on a semi-insulated GaAs substrate were prepared in oxalic acid aqueous solutions by three-step anodization. The I-t curve of anodization process was recorded to observe time effects of anodization. Atomic force microscopy was used to investigate structure and morphology of alumina films. It was revealed that the case of oxalic acid resulted in a self-ordered porous structure, with the pore diameters of 60-70 nm, the pore density of the order of about 10(10) pore cm(-2), and interpore distances of 95-100nm. At the same time the pore size and shape change with the pore widening time. Field-enhanced dissolution model and theory of deformation relaxation combined were brought forward to be the cause of self-ordered pore structure according to I-t curve of anodization and structure characteristics of porous alumina films. (c) 2006 Elsevier Ltd. All rights reserved.

Behavior model of a CMOS process compatible photo-diode

A behavior model of a photo-diode is presented. The model describes the relationship between photocurrent and incident optical power, and it also illustrates the impact of the reverse bias to the variation of the junction capacitance. With this model, the photo-diode and a CMOS receiver circuit were simulated and designed simultaneously under a universal circuit simulation environment.

Improvement of the electrical property of semi-insulating InP by suppression of compensation defects

Semi-insulating (SI) InP obtained by iron phosphide ambient annealing has very low concentration of deep level defects and better electrical property than SI-InP annealed in phosphorus ambient. The defect suppression phenomenon correlates with Fe diffusion and substitution in the annealing process. Analysis of the experimental result suggests that a high activation ratio of incorporated Fe in InP has an effect of defect suppression in Fe-doped and Fe-diffused SI-InP.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

a flexible negotiation model for an agent-based software process modelling

Our Agent-based Software Process Modelling (ASPM) approach describes a software process as a set of cooperative agents. Negotiation is the way in which the agents construct their cooperative relations, and thus the software process. Currently, most negotiation models use a fixed negotiation protocol and fixed strategies. In order to achieve the flexibility that the negotiation of the agents in ASPM requires, we propose a negotiation model NM-PA. NM-PA mainly includes a generic negotiation protocol and some rules, which possibly change in different negotiation processes. By changing the rules, the model can support multi-protocols and multi-decision-making strategies at a lower cost.