Ancients inspire modern memory

A stencilling technique for depositing arrays of nanoscale ferroelectric capacitors on a surface could be useful in data storage devices.

Liquid source misted chemical deposition process of three-dimensional nano-ferroelectrics with substrate heating

A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O-3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650 degrees C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs

.In this letter, we demonstrate for the first time that gate misalignment is not a critical limiting factor for low voltage operation in gate-underlap double gate (DG) devices. Our results show that underlap architecture significantly extends the tolerable limit of gate misalignment in 25 nm devices. DG MOSFETs with high degree of gate misalignment and optimal gate-underlap design can perform comparably or even better than self-aligned nonunderlap devices. Results show that spacer-to-straggle (s/sigma) ratio, a key design parameter for underlap devices, should be within the range of 2.3-3.0 to accommodate back gate misalignment. These results are very significant as the stringent process control requirements for achieving self-alignment in nanoscale planar DG MOSFETs are considerably relaxed

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Hydroisomerisation of n-alkanes over partially reduced MoO3: Promotion by CoAlPO-11 and relations to reaction mechanism and rate-determining step

The reaction mechanism and the rate-determining step (RDS) of the isomerisation of n-alkanes (C-4-C-6) over partially reduced MoO3 catalysts were studied through the effects of the addition of an alkene isomerisation catalyst (i.e. CoAlPO- 11). When an acidic CoAlPO- 11 sample was mechanically mixed with the MoO3, a decrease of the induction period and an increase of the steady-state conversion of n-butane to isobutane were observed. These data support previous assumptions that a bifunctional mechanism occurred over the partially reduced MoO3 (a complex nanoscale mixture of oxide-based phases) during n-butane isomerisation and that the RDS was the skeletal isomerisation of the linear butene intermediates. The only promotional effect of CoAlPO-11 on the activity of partially reduced MoO3 for C-5-C-6 alkane hydroisomerisation was a reduction of the induction period, as the RDS at steady-state conditions appeared to be dehydrogenation of the alkane in this case. However, lower yields of branched isomers were observed in this case, the reason of which is yet unclear. (c) 2005 Elsevier B.V. All rights reserved.

Origin of Ferroelastic domains in Free-Standing Single Crystal Ferroelectric Films

The origin of the unusual 90 degrees ferroelectric/ferroelastic domains, consistently observed in recent studies on mesoscale and nanoscale free-standing single crystals of BaTiO3 [Schilling , Phys. Rev. B 74, 024115 (2006); Schilling , Nano Lett. 7, 3787 (2007)], has been considered. A model has been developed which postulates that the domains form as a response to elastic stress induced by a surface layer which does not undergo the paraelectric-ferroelectric cubic-tetragonal phase transition. This model was found to accurately account for the changes in domain periodicity as a function of size that had been observed experimentally. The physical origin of the surface layer might readily be associated with patterning damage, seen in experiment; however, when all evidence of physical damage is removed from the BaTiO3 surfaces by thermal annealing, the domain configuration remains practically unchanged. This suggests a more intrinsic origin, such as the increased importance of surface tension at small dimensions. The effect of surface tension is also shown to be proportional to the difference in hardness between the surface and the interior of the ferroelectric. The present model for surface-tension induced twinning should also be relevant for finely grained or core-shell structured ceramics.

Domains in Ferroelectric Nanodots

Almost free-standing single crystal mesoscale and nanoscale dots of ferroelectric BaTiO3 have been made by direct focused ion beam patterning of bulk single crystal material. The domain structures which appear in these single crystal dots, after cooling through the Curie temperature, were observed to form into quadrants, with each quadrant consisting of fine 90° stripe domains. The reason that these rather complex domain configurations form is uncertain, but we consider and discuss three possibilities for their genesis: first, that the quadrant features initially form to facilitate field-closure, but then develop 90° shape compensating stripe domains in order to accommodate disclination stresses; second, that they are the result of the impingement of domain packets which nucleate at the sidewalls of the dots forming “Forsbergh” patterns (essentially the result of phase transition kinetics); and third, that 90° domains form to conserve the shape of the nanodot as it is cooled through the Curie temperature but arrange into quadrant packets in order to minimize the energy associated with uncompensated surface charges (thus representing an equilibrium state). While the third model is the preferred one, we note that the second and third models are not mutually exclusive.

Casting of Self-Compacting Concrete

Increased productivity and improved working environment have had high priority in the development of concrete construction over the last decade. Development of a material not needing vibration for compaction—i.e. selfcompacting concrete (SCC)—has successfully met the challenge and is now increasingly being used in routine practice. The key to the improvement of fresh concrete performance has been nanoscale tailoring of molecules for surface active admixtures, as well as improved understanding of particle packing and of the role of mineral surfaces in cementitious matrixes. Fundamental studies of rheological behaviour of cementitious particle suspensions were soon expanded to extensive innovation programmes incorporating applied research, site experiments, instrumented full scale applications supporting technology, standards and guides, information efforts as well as training programmes. The major impact of the introduction of SCC is connected to the production process. The choice and handling of constituents are modified as well as mix design, batching, mixing and transporting. The productivity is drastically improved through elimination of vibration compaction and process reorganisation. The working environment is significantly enhanced through avoidance of vibration induced damages, reduced noise and improved safety. Additionally, the technology is improving performance in terms of hardened material properties like surface quality, strength and durability.

Small angle neutron scattering from 1-alkyl-3-methylimidazolium hexafluorophosphate ionic liquids ([C(n)mim][PF6], n=4, 6, and 8)

The presence of local anisotropy in the bulk, isotropic, and ionic liquid phases-leading to local mesoscopic inhomogeneity-with nanoscale segregation and expanding nonpolar domains on increasing the length of the cation alkyl-substituents has been proposed on the basis of molecular dynamics (MD) simulations. However, there has been little conclusive experimental evidence for the existence of intermediate mesoscopic structure between the first/second shell correlations shown by neutron scattering on short chain length based materials and the mesophase structure of the long chain length ionic liquid crystals. Herein, small angle neutron scattering measurements have been performed on selectively H/D-isotopically substituted 1-alkyl-3-methylimidazolium hexafluorophosphate ionic liquids with butyl, hexyl, and octyl substituents. The data show the unambiguous existence of a diffraction peak in the low-Q region for all three liquids which moves to longer distances (lower Q), sharpens, and increases in intensity with increasing length of the alkyl substituent. It is notable, however, that this peak occurs at lower values of Q (longer length scale) than predicted in any of the previously published MD simulations of ionic liquids, and that the magnitude of the scattering from this peak is comparable with that from the remainder of the amorphous ionic liquid. This strongly suggests that the peak arises from the second coordination shells of the ions along the vector of alkyl-chain substituents as a consequence of increasing the anisotropy of the cation, and that there is little or no long-range correlated nanostructure in these ionic liquids.

Modelling non-adiabatic processes using correlated electron-ion dynamics

Here we survey the theory and applications of a family of methods (correlated electron-ion dynamics, or CEID) that can be applied to a diverse range of problems involving the non-adiabatic exchange of energy between electrons and nuclei. The simplest method, which is a paradigm for the others, is Ehrenfest Dynamics. This is applied to radiation damage in metals and the evolution of excited states in conjugated polymers. It is unable to reproduce the correct heating of nuclei by current carrying electrons, so we introduce a moment expansion that allows us to restore the spontaneous emission of phonons. Because of the widespread use of Non-Equilibrium Green's Functions for computing electric currents in nanoscale systems, we present a comparison of this formalism with that of CEID with open boundaries. When there is strong coupling between electrons and nuclei, the moment expansion does not converge. We thus conclude with a reworking of the CEID formalism that converges systematically and in a stable manner.