Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是兰州重离子加速器冷却储存环（HIRFL-CSR）注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。踢轨磁铁（Kicker）电源系统各触发脉冲是否同步关系到束流能否顺利注入引出以及有好的束流品质。基于此，本文介绍了基于CPLD-EPM1270T144的数字延迟线系统，以满足HIRFL-CSR踢轨磁铁（Kicker）电源对触发脉冲进行适当延迟的要求；分析介绍了数字延迟线系统结构、工作原理、PCB制版及系统调试。实际检验证明本设计通过修改VHDL程序来调节延迟时间能够方便灵活的完成Kicker电源系统对脉冲同步的要求，延迟精度达到10ns。另外，由于Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns、脉冲宽度为650ns,其脉冲峰值电流为2700A、工作周期为10s-17s，因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性非常重要。基于此，本文还进行了Kicker电源监测系统的设计。该设计主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的系统结构、工作原理，并完成了程序编程、仿真及外围电路设计

SDRAM控制器的设计及其在CSR控制系统中的应用

在国家重大科学工程HIRFL-CSR的控制系统中，高速数据获取单元或非线性过程控制器常用到数据缓冲存储器。采用集成度高、功耗低、可靠性高、处理能力强的同步动态随机存储器SDRAM，是最好的选择。但是，与速度快、控制简单的SRAM相比，SDRAM存储器有复杂的时序要求，需要定时刷新，为此，必须设计SDRAM控制器。为了降低系统成本，采用FPGA技术，并使用VHDL语言设计和实现SDRAM控制器。论文首先介绍了存储器的结构和原理，SDRAM控制器的结构和组成，FPGA技术及其配置方法和VHDL语言的基本概念。随后详细介绍了SDRAM控制器基本结构的建立、符合PC133规范的硬件设计方案和软件的实现。其次，介绍了串口和SDRAM控制器的设计开发平台，并实现对SDRAM存储器的数据读写和刷新。另外，还介绍了与计算机进行串口通信的设计。 最后，介绍了利用FPGA实现DSP与SDRAM的接口电路设计及其在HIRFL-CsR控制系统中的应用。整个论文的工作完成了CSR控制系统中SDRAM控制器的硬件设计和VHDL程序编制、调试。为以后开发和实现控制系统的高速数据获取提供了一个原型。

一种FPGA的嵌入式可重构机器人控制系统

提出一种基于FPGA的可重构嵌入式微处理器控制系统.在FPGA中嵌入两个NiosⅡ软核,用VHDL语言编写用户自定义组件.在一个由NiosⅡ软核组成的处理器上实现PWM信号生成、编码器信号处理以及多电机同步伺服运算等,在另一个处理器实现机器人任务管理.该控制系统针对微小型爬壁机器人的控制系统设计,不仅具有良好的实时多任务处理能力,而且具有可重构的特点,因而可应用于一类微小型机器人控制系统以提高其设计的灵活性.

智能相机在激光焊缝跟踪检测系统中的应用研究

本文以中国科学院知识创新工程重要方向项目“全自动激光拼焊成套装备关键技术研究与示范应用”及沈阳市科技攻关项目“激光视觉焊缝自动跟踪与质量检测系统”为依托，针对激光焊接这个难点问题，在广泛调研国内外研究现状的基础上，研究开发了一套激光视觉焊缝跟踪检测原理样机。本文主要包括以下四方面的工作：1焊缝跟踪系统的系统结构搭建；2图像处理方法研究；3图像处理方法在FPGA中的实现；4基于工业机器人的激光焊接实验 及结果分析。具体工作如下： 本文首先论述了应用于焊缝跟踪的线结构光视觉传感器检测原理，建立了激光焊缝跟踪检测系统实验平台。该平台由图像采集与处理模块、上位机系统、DSP控制器、伺服电机驱动器、伺服电机等五部分组成。 激光拼焊焊缝跟踪图像的处理方法是关键技术之一，直接影响系统的实时性，根据激光拼焊焊缝跟踪图像的特点设计了相应的图像处理算法，分析研究了基于数学形态学的焊缝跟踪结构光条纹图像增强算法，并根据本课题的特点提出了一种基于模板的边缘提取方法，能简洁快速地提取出单像素边缘，然后研究了结构光中心线提取算法以及焊缝特征点识别算法，最后通过仿真实验验证了该图像处理流程的有效性。 论文的重点在于图像处理方法在智能相机中的实时实现。跟踪系统对图像处理的实时性要求很高，传统的处理方法主要是在DSP中以软件编程的方式实现，速度难以进一步提高，本课题中通过在智能相机中的FPGA中构建一个SOPC系统，将基于硬件描述语言VHDL完成的图像预处理模块和基于Xilinx公司的microblaze软核的特征点提取模块集成在单片芯片上，实现了激光条纹特征点的实时提取，系统具有高度的灵活性与出色的功能。 最后对搭建的跟踪系统平台进行了实验研究，用实验验证了焊缝跟踪系统的性能，保证了该套系统能够满足实时跟踪的要求，可以达到预期的设计目标。

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

High-performance 3D median filter architecture for medical image despeckling

A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

Rapid design of biorthogonal wavelet transforms

A rapid design methodology for biorthogonal wavelet transform cores has been developed based on a generic, scaleable architecture for wavelet filters. The architecture offers efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation in a MAC-based implementation. The design has been captured in VHDL and parameterised in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet system is typically less than a day. The silicon cores produced are comparable in area and performance to hand-crafted designs, The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Rapid design of discrete orthonormal wavelet transforms

A methodology which allows a non-specialist to rapidly design silicon wavelet transform cores has been developed. This methodology is based on a generic architecture utilizing time-interleaved coefficients for the wavelet transform filters. The architecture is scaleable and it has been parameterized in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is designed in such a way that the cores can also be cascaded without any interface glue logic for any desired level of decomposition. This parameterization allows the use of any orthonormal wavelet family thereby extending the design space for improved transformation from algorithm to silicon. Case studies for stand alone and cascaded silicon cores for single and multi-stage analysis respectively are reported. The typical design time to produce silicon layout of a wavelet based system has been reduced by an order of magnitude. The cores are comparable in area and performance to hand-crafted designs. The designs have been captured in VHDL so they are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Rapid silicon design of discrete orthonormal wavelet transforms based algorithms

A methodology has been developed which allows a non-specialist to rapidly design silicon wavelet transform cores for a variety of specifications. The cores include both forward and inverse orthonormal wavelet transforms. This methodology is based on efficient, modular and scaleable architectures utilising time-interleaved coefficients for the wavelet transform filters. The cores are parameterized in terms of wavelet type and data and coefficient word lengths. The designs have been captured in VHDL and are hence portable across a range of silicon foundries as well as FPGA and PLD implementations.

Rapid VLSI design of biorthogonal wavelet transform cores

A rapid design methodology for biorthogonal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture for the wavelet filters. The architecture offers efficient hardware utilization by combining the linear phase property of biorthogonal filters with decimation in a MAC based implementation. The design has been captured in VHDL and parameterized in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet based system is typically less than a day. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Synthesizable high performance adaptive equaliser and viterbi decoder for the class-IV PRML channel

The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

Rapid design of discrete orthonormal wavelet transforms using silicon IP components

A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved coefficients for the wavelet transform filters. The architecture has been captured in VHDL and parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. Case studies for stand alone and cascaded silicon cores for single and multi-stage wavelet analysis respectively are reported. The design time to produce silicon layout of a wavelet based system has been reduced to typically less than a day. The cores are comparable in area and performance to handcrafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Quantization effects in the polyphase N-path IIR structure

Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mathematical description is very simple, there exist a number of ways to implement such filters. In this paper, we take four of these different implementation structures, analyze the rounding noise originating from the limited arithmetic wordlength of the mathematical operators, and check the internal data growth within the structure. These analyses need to be done to ensure that the performance of the implementation matches the performance of the theoretical design. The theoretical approach that we present has been proven by the results of the fixed-point simulation done in Simulink and verified by an equivalent bit-true implementation in VHDL.

Design and low-power implementation of an adaptive image rejection receiver

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures.