Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

High-speed electrooptical VOA integrated in silicon-on-insulator

In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) inte-grated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption toachieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simu-lation tool PISCES-Ⅱ were used to analyze the dc and transient characteristics of the device. The devicehas a response time (including rise time and fall time) less than 200 ns, much faster than the thermoopticand micro-electromechanical systems (MEMSs) based VOAs.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Electrical characteristics of copper phthalocyanine thin-film transistors with polyamide-6/polytetrafluoroethylene gate insulator

Polyamide- 6(PA 6)/polytetrafluoroethylene is studied as a potential gate dielectric for flexible organic thin film transistors. The same method used for the formation of organic semiconductor and gate dielectric films greatly simplifies the fabrication process of devices. The fabricated transistors show good electrical characteristics. Ambipolar behaviour is observed even when the device is operated in air.

THEORY OF ELECTRICAL CHARACTERISTICS OF A SCHOTTKY-BARRIER HAVING EXPONENTIALLY DISTRIBUTED IMPURITY STATES AND METAL-INSULATOR METAL STRUCTURES

The metal-insulator or metal-amorphous semiconductor blocking contact is still not well understood. Here, we discuss the steady state characteristics of a non-intimate metal-insulator Schottky barrier. We consider an exponential distribution (in energy) of impurity states in addition to impurity states at a single energy level within the depletion region. We present analytical expressions for the electrical potential, field, thickness of depletion region, capacitance, and charge accumulated in the depletion region. We also discuss ln I versus V(ap) data. Finally, we compare the characteristics in three cases: (i) impurity states at only a single energy level; (ii) uniform energy distribution of impurity states; and (iii) exponential energy distribution of impurity states.In general, the electrical characteristics of Schottky barriers and metal-insulator-metal structures with Schottky barriers depend strongly on the energy distribution of impurity states.

THEORY OF NON-STEADY-STATE ELECTRICAL CHARACTERISTICS OF METAL-INSULATOR-METAL STRUCTURES WITH SCHOTTKY BARRIERS AND UNIFORMLY DISTRIBUTED INTERFACE IMPURITY STATES

The metal-insulator (or amorphous semiconductor) blocking contact is still not well understood. In the present paper, we discuss the non steady state characteristics of Metal-lnsulator-Metal Structure with non-intimate blocking contacts (i.e. Metal-Oxide-Insulator-Metal Structure). We consider a uniform distribution (in energy) of impurity states in addition to impurity states at a single energy level within the depletion region. We discuss thermal as well as isothermal characteristics and present expressions for the temperature of maximum current (T-m) and a method to calculate the density of uniformly distributed impurity states. The variation of mobility with electrical field has also been considered. Finally we plot the theoretical curves under different conditions. The present results are closing into available experimental results.

Theory of electrical characteristics for metal-oxide-insulator Schottky barrier and metal-insulator-metal structures

The metal-insulator or metal-amorphous semiconductor blocking contact is still not well understood. Here, the intimate metal-insulator and metal-oxide-insulator contact are discussed. Further, the steady-state characteristics of metal-oxide-insulator-metal structures are also discussed. Oxide is an insulator with wider energy band gap (about 50 Å thick). A uniform energetic distribution of impurities is considered in addition to impurities at a single energy level inside the surface charge region at the oxide-insulator interface. Analytical expressions are presented for electrical potential, field, thickness of the depletion region, capacitance, and charge accumulated in the surface charge region. The electrical characteristics are compared with reference to relative densities of two types of impurities. ln I is proportional to the square root of applied potential if energetically distributed impurities are relatively important. However, distribution of the electrical potential is quite complicated. In general energetically distributed impurities can considerably change the electrical characteristics of these structures.

Insulator-to-metal transition driven by clustering of solitons in polyacetylene

It's believed that the simple Su-Schrieffer-Heeger Hamiltonian can not predict the insulator to metal transition of transpolyacetylene (t-PA). The soliton lattice configuration at a doping level y=6% still has a semiconductor gap. Disordered distributions of solitons close the gap, but the electronic states around the Fermi energy are localized. However, within the same framework, it is possible to show that a cluster of solitons can produce dramatic changes in the electronic structure, allowing an insulator-to-metal transition.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Impedance analysis of Al2O3/H-terminated diamond metal-oxide-semiconductor structures

Impedance spectroscopy (IS) analysis is carried out to investigate the electrical properties of the metal-oxide-semiconductor (MOS) structure fabricated on hydrogen-terminated single crystal diamond. The low-temperature atomic layer deposition Al2O3 is employed as the insulator in the MOS structure. By numerically analysing the impedance of the MOS structure at various biases, the equivalent circuit of the diamond MOS structure is derived, which is composed of two parallel capacitive and resistance pairs, in series connection with both resistance and inductance. The two capacitive components are resulted from the insulator, the hydrogenated-diamond surface, and their interface. The physical parameters such as the insulator capacitance are obtained, circumventing the series resistance and inductance effect. By comparing the IS and capacitance-voltage measurements, the frequency dispersion of the capacitance-voltage characteristic is discussed.