Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

In-situ Boron-doped Low-stress LPCVD Polysilicon for Micromechanical Disk Resonator

Polycrystalline silicon (polysilicon) has been used as an important structural material for microelectro-mechnical systems (MEMS) because of its compatibility with standard integrated circuit (IC) processes. As the structural layer of micromechanical high resonance frequency (high-f) and high quality factor (high-Q) disk resonators, the low residual stress and low resistivity are desired for the polysilicon thin films. In the present work, we investigate the effect of deposition and annealing conditions on the residual stress and resistivity for in-situ deposited low pressure chemical vapor deposition (LPCVD) polysilicon films. Low residual stress (-100 MPa) was achieved in in-situ boron-doped polysilicon films deposited at 570 degrees C and annealed at 1000 degrees C for 4 hr. The as-deposited amorphous polysilicon films were crystallized by the rapid thermal annealing and have the (111)-preferred orientation, the low tensile residual stress is expected for this annealed film, the detailed description on this work will be reported soon. The controllable residual stress and resistivity make these films suitable for high-Q and bigh-f micro-mechanical disk resonators.

Simulation and fabrication of the SiC-based clamped-clamped filter

In this paper, the SiC-based clamped-clamped filter was designed and fabricated. The filter was composed of two clamped-clamped beam micromechanical resonators coupled by a spring coupling beam. Structural geometries, including the length and width of the resonator beam and coupling beam, were optimized by simulation for high frequency and high Q, under the material properties of SiC. The vibrating modes for the designed filter structure were analyzed by finite element analysis (FEA) method. For the optimized structure, the geometries of resonator beams and coupling beams, as well as the coupling position, the SiC-based clamped-clamped filter was fabricated by surface micromaching technology.

Application of ICA in on-line verification of the phase difference of the current sensor

The performance of the current sensor in power equipment may become worse affected by the environment. In this paper, based on ICA, we propose a method for on-line verification of the phase difference of the current sensor. However, not all source components are mutually independent in our application. In order to get an exact result, we have proposed a relative likelihood index to choose an optimal result from different runs. The index is based on the maximum likelihood evaluation theory and the independent subspace analysis. The feasibility of our method has been confirmed by experimental results.

Study on text-dependent speaker recognition based on Biomimetic Pattern Recognition

We studied the application of Biomimetic Pattern Recognition to speaker recognition. A speaker recognition neural network using network matching degree as criterion is proposed. It has been used in the system of text-dependent speaker recognition. Experimental results show that good effect could be obtained even with lesser samples. Furthermore, the misrecognition caused by untrained speakers occurring in testing could be controlled effectively. In addition, the basic idea "cognition" of Biomimetic Pattern Recognition results in no requirement of retraining the old system for enrolling new speakers.

High-Dimensional Space Geometrical Informatics and its applications to image restoration

With a view to solve the problems in modern information science, we put forward a new subject named High-Dimensional Space Geometrical Informatics (HDSGI). It builds a bridge between information science and point distribution analysis in high-dimensional space. A good many experimental results certified the correctness and availability of the theory of HDSGI. The proposed method for image restoration is an instance of its application in signal processing. Using an iterative "further blurring-debluring-further blurring" algorithm, the deblured image could be obtained.

Research on multi-degree-of-freedom neurons with weighted graphs

In this paper, we redefine the sample points set in the feature space from the point of view of weighted graph and propose a new covering model - Multi-Degree-of-Freedorn Neurons (MDFN). Base on this model, we describe a geometric learning algorithm with 3-degree-of-freedom neurons. It identifies the sample points secs topological character in the feature space, which is different from the traditional "separation" method. Experiment results demonstrates the general superiority of this algorithm over the traditional PCA+NN algorithm in terms of efficiency and accuracy.

Optical analysis of AlGaInP laser diodes with real refractive index guided self-aligned structure

Optical modes of AlGaInP laser diodes with real refractive index guided self-aligned (RISA) structure were analyzed theoretically on the basis of two-dimension semivectorial finite-difference methods (SV-FDMs) and the computed simulation results were presented. The eigenvalue and eigenfunction of this two-dimension waveguide were obtained and the dependence of the confinement factor and beam divergence angles in the direction of parallel and perpendicular to the pn junction on the structure parameters such as the number of quantum wells, the Al composition of the cladding layers, the ridge width, the waveguide thickness and the residual thickness of the upper P-cladding layer were investigated. The results can provide optimized structure parameters and help us design and fabricate high performance AlGaInP laser diodes with a low beam aspect ratio required for optical storage applications.

Effect of SiO2 encapsulation on the nitrogen reorganization in GaNAs/GaAs single quantum well

Effects of SiO2, encapsulation and rapid thermal annealing (RTA) on the optical properties of GaNAs/GaAs single quantum well (SQW) were studied by low temperature photoluminescence (PL). A blueshift of the PL peak energy for both the SiO2-capped region and the bare region was observed. The results were attributed to the nitrogen reorganization in the GaNAs/GaAs SQW. It was also shown that the nitrogen reorganization was obviously enhanced by SiO2 cap-layer. A simple model [1] was used to describe the SiO2-enhanced blueshift of the low temperature PL peak energy.