935 resultados para negotiation with Chinese
Resumo:
GaN nanorods with vertebra-like morphology were synthesized by nitriding Ga2O3/ZnO films at 1000 degrees C for 20min. Ga2O3 thin films and ZnO middle layers were pre-deposited in turn on Si(111) substrates by r.f. magnetron sputtering system. In the flowing ammonia ambient, ZnO was reducted to Zn and Zu sublimated at 1000 degrees C. Ga2O3 was reducted to Ga2O and Ga2O reacted with NH3 to synthesize GaN nanorods in the help of the sublimation of Zn. The structure and morphology of the nanorods were studied by X-ray diffraction (XRD) and scanning electron microscopy (SEM), The composition of GaN nanorods was studied by energy dispersive spectroscopy (EDS) and fourier transform infrared (FTIR) system.
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We used Plane Wave Expansion Method and a Rapid Genetic Algorithm to design two-dimensional photonic crystals with a large absolute band gap. A filling fraction controlling operator and Fourier transform data storage mechanism had been integrated into the genetic operators to get desired photonic crystals effectively and efficiently. Starting from randomly generated photonic crystals, the proposed RGA evolved toward the best objectives and yielded a square lattice photonic crystal with the band gap (defined as the gap to mid-gap ratio) as large as 13.25%. Furthermore, the evolutionary objective was modified and resulted in a satisfactory PC for better application to slab system.
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A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.
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In this paper, we propose a new scheme for omnidirectional object-recognition in free space. The proposed scheme divides above problem into several onmidirectional object-recognition with different depression angles. An onmidirectional object-recognition system with oblique observation directions based on a new recognition theory-Biomimetic Pattern Recognition (BPR) is discussed in detail. Based on it, we can get the size of training samples in the onmidirectional object-recognition system in free space. Omnidirection ally cognitive tests were done on various kinds of animal models of rather similar shapes. For the total 8400 tests, the correct recognition rate is 99.89%. The rejection rate is 0.11% and on the condition of zero error rates. Experimental results are presented to show that the proposed approach outperforms three types of SVMs with either a three degree polynomial kernel or a radial basis function kernel.
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A SOI-based thermo-optic waveguide switch matrix worked at 1.55 mu m, integrated with spot size converters is designed and fabricated for the first time. The insertion loss and polarization dependent loss are less than 13dB and 2dB, respectively. The extinction ratio is larger than 19dB. The response time is less than 5 mu s and the power consumption of the switch cell is about 200mW.
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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).
Resumo:
A 1.55-mu m ridge DFB laser and electroabsorption modulator monolithically integrated with a buried-ridge-stripe dual-waveguide spot-size converter at the output port for low-loss coupling to a cleaved single-mode optical fiber was fabricated by means of selective area growth, quantum well intermixing and dual-core technologies. These devices exhibit threshold current of 28 mA, side mode suppression ratio of 38.0 dB, 3-dB modulation bandwidth of 12.0 GHz, modulator extinction ratios of 25.0 dB dc. The output beam divergence angles of the spot-size converter in the horizontal and vertical directions are as small as 8.0 degrees x 12.6 degrees, respectively, resulting in 3.2 dB coupling loss with a cleaved single-mode optical fiber.
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A novel device of tandem multiple quantum wells (MQWs) electroabsorption modulators (EAMs) monolithically integrated with DFB laser is fabricated by ultra-low-pressure (22 mbar) selective area guowth (SAG) MOCVD technique. Experimental results exhibit superior device characteristics with low threshold of 19 mX output light power of 4.5 mW and over 20 dB extinction ratio when coupled into a single mode Fiber. Moreover, over 10 GHz modulation bandwidth is developed with a driving voltage of 2 V. Using I this sinusoidal voltage driven integrated device, 10GHz repetition rate pulse with a width of 13.7 ps without any compression elements is obtained.
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Width varied quantum wells show a more flat and wide gain spectrume (about 115nm) than that of identical miltiple quantum well. A new fabricating method was demonstrated in this paper to realize two different Bragg grating in an selectable DFB laser based on this material grown identical chip using traditional holographic exposure. A wavelength by MOVPE was presented. Two stable distinct single longitudinal mode of 1510nm and 1530nm with SMSR of 45 dB were realized.
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Fe-doped semi-insulating (SI) InP has become semi-conducting (SC) material completely after annealing at 900 V for 10 hours. Defects in the SC and SI InP materials have been studied by deep level transient spectroscopy (DLTS) and thermally stimulated current spectroscopy (TSC) respectively. The DLTS only detected Fe acceptor related deep level defect with significant concentration, suggesting the formation of a high concentration of shallow donor in the SC-InP TSC results confirmed the nonexistence of deep level defects in the annealed SI-InP. The results demonstrate a significant influence of the thermally induced defects on the electrical properties of SI-InP. The formation mechanism and the nature of the shallow donor defect have been discussed based on the results.
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One novel neuron with variable nonlinear transfer function is firstly proposed, It could also be called as subsection transfer function neuron. With different transfer function components, by virtue of multi-thresholded, the variable transfer function neuron switch on among different nonlinear excitated state. And the comparison of output's transfer characteristics between it and single-thresholded neuron will be illustrated, with some practical application experiments on Bi-level logic operation, at last the simple comparison with conventional BP, RBF, and even DBF NN is taken to expect the development foreground on the variable neuron.. The novel nonlinear transfer function neuron could implement the random nonlinear mapping relationship between input layer and output layer, which could make variable transfer function neuron have one much wider applications on lots of reseach realm such as function approximation pattern recognition data compress and so on.
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This paper represents a LC VCO with AAC (Auto Amplitude Control), in which PMOS FETs are used as active components, and the varactors are directly connected to ground to widen Kvco linear range. The AAC circuitry adds little noise to the VCO and provides it with robust performance over a wide temperature and carrier frequency range. The VCO is fabricated in 50-GHz 0.35-mu m SiGe BiCMOS process. The measurement results show that it has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole circuit draws 6.6-mA current from 5.0-V supply.
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Hydrogenated nanocrystalline silicon (nc-Si:H) n-layers have been used to prepare heterojunction solar cells on flat p-type crystalline silicon (c-Si) wafers. The nc-Si:H n-layers were deposited by radio-frequency (RF) plasma enhanced chemical vapor deposition (PECVD), and characterized using Raman spectroscopy, optical transmittance and activation energy of dark-conductivity. The nc-Si:H n-layers obtained comprise fine grained nanocrystallites embedded in amorphous matrix, which have a wider bandgap and a smaller activation energy. Heterojunction solar cells incorporated with the nc-Si n-layer were fabricated using configuration of Ag (100 nm)/1T0 (80 nm)/n-nc-Si:H (15 nm)/buffer a-Si:H/p-c-Si (300 mu m)/Al (200 nm), where a very thin intrinsic a-Si:H buffer layer was used to passivate the p-c-Si surface, followed by a hydrogen plasma treatment prior to the deposition of the thin nanocrystalline layer. The results show that heterojunction solar cells subjected to these surface treatments exhibit a remarkable increase in the efficiency, up to 14.1% on an area of 2.43 cm(2). (c) 2006 Elsevier B.V. All rights reserved.
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In this paper, we redefine the sample points set in the feature space from the point of view of weighted graph and propose a new covering model - Multi-Degree-of-Freedorn Neurons (MDFN). Base on this model, we describe a geometric learning algorithm with 3-degree-of-freedom neurons. It identifies the sample points secs topological character in the feature space, which is different from the traditional "separation" method. Experiment results demonstrates the general superiority of this algorithm over the traditional PCA+NN algorithm in terms of efficiency and accuracy.
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This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.