972 resultados para SILICON HETEROJUNCTION


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Amorphous SiC(x)N(y) films have been deposited on (100) Si substrates by RF magnetron sputtering of a SiC target in a variable nitrogen-argon atmosphere. The as-deposited films were submitted to thermal anneling in a furnace under argon atmosphere at 1000 degrees C for 1 hour. Composition and structure of unannealed and annealed samples were investigated by RBS and FTIR. To study the electrical characteristics of SiC(x)N(y) films, Metal-insulator-semiconductor (MIS) structures were fabricated. Elastic modulus and hardness of the films were determined by nanoindentation. The results of these studies showed that nitrogen content and thermal annealing affect the electrical, mechanical and structural properties of SiC(x)N(y) films.

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This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

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The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.

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In this work we present the fabrication and operation of incandescent microlamps for integrated optics applications. This microlamp emits white and infrared light from a chromium resistor embedded in a free-standing silicon oxynitride (SiO(x)N(y)) cantilever that can be coupled to an optical waveguide. In fact, the chromium resistor is sandwiched between layers of SiO(x)N(y) that isolate it from the atmosphere, while electric current heats the resistor to incandescent temperatures. The same SiO(x)N(y) material used in the microlamp fabrication is also used to produce the optical waveguides to allow a monolithic integration of light source and optical circuit. Front-side bulk micromachining of the silicon substrate in potassium hydroxide (KOH) solution is used to fabricate the cantilevers that thermally isolate the resistors from the substrate, thus reducing the heat transfer and the current required to light the lamp.

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Over the last decades, anti-resonant reflecting optical waveguides (ARROW) have been used in different integrated optics applications. In this type of waveguide, light confinement is partially achieved through an anti-resonant reflection. In this work, the simulation, fabrication and characterization of ARROW waveguides using dielectric films deposited by a plasma-enhanced chemical vapor deposition (PECVD) technique, at low temperatures(similar to 300 degrees C), are presented. Silicon oxynitride (SiO(x)N(y)) films were used as core and second cladding layers and amorphous hydrogenated silicon carbide(a-SiC:H) films as first cladding layer. Furthermore, numerical simulations were performed using homemade routines based on two computational methods: the transfer matrix method (TMM) for the determination of the optimum thickness of the Fabry-Perot layers; and the non-uniform finite difference method (NU-FDM) for 2D design and determination of the maximum width that yields single-mode operation. The utilization of a silicon carbide anti-resonant layer resulted in low optical attenuations, which is due to the high refractive index difference between the core and this layer. Finally, for comparison purposes, optical waveguides using titanium oxide (TiO(2)) as the first ARROW layer were also fabricated and characterized.

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Silicon carbide thin films (Si(x)C(y)) were deposited in a RF (13.56 MHz) magnetron sputtering system using a sintered SiC target (99.5% purity). In situ doping was achieved by introducing nitrogen into the electric discharge during the growth process of the films. The N(2)/Ar flow ratio was adjusted by varying the N(2) flow rate and maintaining constant the Ar flow rate. The structure, composition and bonds formed in the nitrogen-doped Si (x) C (y) thin films were investigated by X-ray diffraction (XRD), Rutherford backscattering spectroscopy (RBS), Raman spectroscopy and Fourier transform infrared spectrometry (FTIR) techniques. RBS results indicate that the carbon content in the film decreases as the N(2)/Ar flow ratio increases. Raman spectra clearly reveal that the deposited nitrogen-doped SiC films are amorphous and exhibited C-C bonds corresponding to D and G bands. After thermal annealing, the films present structural modifications that were identified by XRD, Raman and FTIR analyses.

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This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

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The development and fabrication of a thermo-electro-optic sensor using a Mach-Zehnder interferometer and a resistive micro-heater placed in one of the device`s arms is presented. The Mach-Zehnder structure was fabricated on a single crystal silicon substrate using silicon oxynitride and amorphous hydrogenated silicon carbide films to form an anti-resonant reflective optical waveguide. The materials were deposited by Plasma enhanced chemical vapor deposition technique at low temperatures (similar to 320 degrees C). To optimize the heat transfer and increase the device response with current variation, part of the Mach-Zehnder sensor arm was suspended through front-side bulk micromachining of the silicon substrate in a KOH solution. With the temperature variation caused by the micro-heater, the refractive index of the core layer of the optical waveguide changes due to the thermo-optic effect. Since this variation occurs only in one of the Mach-Zehnder`s arm, a phase difference between the arms is produced, leading to electromagnetic interference. In this way, the current applied to the micro-resistor can control the device output optical power. Further, reactive ion etching technique was used in this work to define the device`s geometry, and a study of SF6 based etching rates on different composition of silicon oxynitride films is also presented. (C) 2007 Elsevier B.V. All rights reserved.

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In this work SiOxNy films are produced and characterized. Series of samples were deposited by the plasma enhanced chemical vapor deposition (PECVD) technique at low temperatures from silane (SiH4), nitrous oxide (N2O) and helium (He) precursor gaseous mixtures, at different deposition power in order to analyze the effect of this parameter on the films structural properties, on the SiOxNy/Si interface quality and on the SiOxNy effective charge density. In order to compare the film structural properties with the interface (SiOxNy/Si) quality and effective charge density, MOS capacitors were fabricated using these films as dielectric layer. X-ray absorption near-edge spectroscopy (XANES), at the Si-K edge, was utilized to investigate the structure of the films and the material bonding characteristics were analyzed through Fourier transform infrared spectroscopy (FTIR). The MOS capacitors were characterized by low and high frequency capacitance (C-V) measurements, in order to obtain the interface state density (D-it) and the effective charge density (N-ss). An effective charge density linear reduction for decreasing deposition power was observed, result that is attributed to the smaller amount of ions present in the plasma for low RF power. (C) 2008 Elsevier B.V. All rights reserved.

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In this work, the structure and morphology of silicon oxynitride films deposited by the PECVD technique were studied. The films were deposited under two different conditions: (a) SiOxNy with chemical compositions varying from SiO2 to Si3N4 via the control of a N2O + N-2 + SiH4 gas mixture, and (b) Si-rich SiOxNy films via the control of a N2O + SiH4 gas mixture. The analyses were performed using X-ray near edge spectroscopy (XANES) at the Si-K edge, transmission electron microscopy (TEM) and Rutherford backscattering spectroscopy (RBS). For samples with chemical composition varying from SiO2 to Si3N4, the diffraction patterns obtained by TEM exhibited changes with the chemical composition, in agreement with the XANES results. For silicon-rich silicon oxynitride samples, the formation of a-Si clusters was observed and the possibility of obtaining Si nanocrystals after annealing depending on the composition and temperature was realized. (C) 2007 Elsevier B.V. All rights reserved.

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This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L./W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (R(s)) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both R(s) and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEC ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. (C) 2011 Elsevier Ltd. All rights reserved.

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This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

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A new assessment of the aluminum corner of the quaternary Al-Fe-Mn-Si system has been made that extends beyond the COST-507 database. This assessment makes use of a recent, improved description of the ternary Al-Fe-Si system. In the present work, modeling of the Al-rich corner of the quaternary Al-Fe-Mn-Si system has been carried out by introducing Fe solubility into the so-called alpha-AlMnSi and beta-AlMnSi phases of the Al-Mn-Si system. A critical review of the data available on the quaternary system is presented and used for the extension of the description of these ternary phases into the quaternary Al-Fe-Mn-Si.

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Titanium oxide (TiO(2)) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 degrees C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti(2)O(3), an interfacial SiO(2) layer between the dielectric and the substrate and the anatase crystalline phase of TiO(2) films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO(x)/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10(10)/cm(2) and leakage current density between 1 and 10(-4) A/cm(2). Field-effect transistors were fabricated in order to analyze I(D) x V(DS) and log I(D) x Bias curves. Early voltage value of -1629 V, R(OUT) value of 215 M Omega and slope of 100 mV/dec were determined for the 20 nm TiO(x) film thermally treated at 960 degrees C. (C) 2009 Elsevier B.V. All rights reserved.

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This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.