Laser welding of shape memory alloys

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Mecânica

Sobre o novo em design

Dissertação de Mestrado em Ciências da Comunicação Cultura Contemporânea e Novas Tecnologias

No limite a alma: ensaio sobre um objecto artístico/instalação: trabalho de projecto

Trabalho de Projeto submetido à Escola Superior de Teatro e Cinema para cumprimento dos requisitos necessários à obtenção do grau de Mestre em Teatro - especialização em Design de Cena.

Matrix converter as unified power flow controller: design and implementation of decoupled direct power controllers

This paper presents the design and implementation of direct power controllers for three-phase matrix converters (MC) operating as Unified Power Flow Controllers (UPFC). Theoretical principles of the decoupled linear power controllers of the MC-UPFC to minimize the cross-coupling between active and reactive power control are established. From the matrix converter based UPFC model with a modified Venturini high frequency PWM modulator, decoupled controllers for the transmission line active (P) and reactive (Q) power direct control are synthesized. Simulation results, obtained from Matlab/Simulink, are presented in order to confirm the proposed approach. Results obtained show decoupled power control, zero error tracking, and fast responses with no overshoot and no steady-state error.

High-level Petri nets modules for embedded controllers design

Modular design is crucial to manage large-scale systems and to support the divide-and-conquer development approach. It allows hierarchical representations and, therefore, one can have a system overview, as well as observe component details. Petri nets are suitable to model concurrent systems, but lack on structuring mechanisms to support abstractions and the composition of sub-models, in particular when considering applications to embedded controllers design. In this paper we present a module construct, and an underlying high-level Petri net type, to model embedded controllers. Multiple interfaces can be declared in a module, thus, different instances of the same module can be used in different situations. The interface is a subset of the module nodes, through which the communication with the environment is made. Module places can be annotated with a generic type, overridden with a concrete type at instance level, and constants declared in a module may have a new value in each instance.

Multiobjective design of viscoelastic laminated composite sandwich panels

The optimal design of laminated sandwich panels with viscoelastic core is addressed in this paper, with the objective of simultaneously minimizing weight and material cost and maximizing modal damping. The design variables are the number of layers in the laminated sandwich panel, the layer constituent materials and orientation angles and the viscoelastic layer thickness. The problem is solved using the Direct MultiSearch (DMS) solver for multiobjective optimization problems which does not use any derivatives of the objective functions. A finite element model for sandwich plates with transversely compressible viscoelastic core and anisotropic laminated face layers is used. Trade-off Pareto optimal fronts are obtained and the results are analyzed and discussed.

Optimizing memory transactions for large-scale programs

Even though Software Transactional Memory (STM) is one of the most promising approaches to simplify concurrent programming, current STM implementations incur significant overheads that render them impractical for many real-sized programs. The key insight of this work is that we do not need to use the same costly barriers for all the memory managed by a real-sized application, if only a small fraction of the memory is under contention lightweight barriers may be used in this case. In this work, we propose a new solution based on an approach of adaptive object metadata (AOM) to promote the use of a fast path to access objects that are not under contention. We show that this approach is able to make the performance of an STM competitive with the best fine-grained lock-based approaches in some of the more challenging benchmarks. (C) 2015 Elsevier Inc. All rights reserved.

Design and performance evaluation of turbo FDE receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

Complementary filter design with three frequency bands: robot attitude estimation

This paper extents the by now classic sensor fusion complementary filter (CF) design, involving two sensors, to the case where three sensors that provide measurements in different bands are available. This paper shows that the use of classical CF techniques to tackle a generic three sensors fusion problem, based solely on their frequency domain characteristics, leads to a minimal realization, stable, sub-optimal solution, denoted as Complementary Filters3 (CF3). Then, a new approach for the estimation problem at hand is used, based on optimal linear Kalman filtering techniques. Moreover, the solution is shown to preserve the complementary property, i.e. the sum of the three transfer functions of the respective sensors add up to one, both in continuous and discrete time domains. This new class of filters are denoted as Complementary Kalman Filters3 (CKF3). The attitude estimation of a mobile robot is addressed, based on data from a rate gyroscope, a digital compass, and odometry. The experimental results obtained are reported.

A Influência da teoria da agência na estrutura de capital na indústria do calçado

apresentado ao Instituto de Contabilidade e Administração do Porto para a Dissertação de Mestrado para obtenção do grau de Mestre em Contabilidade e Finanças sob orientação do Mestre Adalmiro Álvaro Malheiro de Castro Andrade Pereira

Light memory operation based on a double pin SiC device

Experimental optoelectronic characterization of a p-i'(a-SiC:H)-n/pi(a-Si:H)-n heterostructure with low conductivity doped layers shows the feasibility of tailoring channel bandwidth and wavelength by optical bias through back and front side illumination. Front background enhances light-to-dark sensitivity of the long and medium wavelength range, and strongly quenches the others. Back violet background enhances the magnitude in short wavelength range and reduces the others. Experiments have three distinct programmed time slots: control, hibernation and data. Throughout the control time slot steady light wavelengths illuminate either or both sides of the device, followed by the hibernation without any background illumination. The third time slot allows a programmable sequence of different wavelengths with an impulse frequency of 6000Hz to shine upon the sensor. Results show that the control time slot illumination has an influence on the data time slot which is used as a volatile memory with the set, reset logical functions. © IFIP International Federation for Information Processing 2015.

Design of a Mobile Application for Eye Signs Screening

Mestrado em Engenharia Computação e Instrumentação Médica

Virtual Communities of Practice: Design and Development of Support Platforms and Participation Fostering

Mestrado em Engenharia Informática - Área de Especialização em Sistemas Gráficos e Multimédia