Sparse matrix multiplication on a reconfigurable many-core architecture
Data(s) |
18/04/2016
18/04/2016
2015
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Resumo |
Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs. |
Identificador |
PINHÃO, João; [et al] - Sparse matrix multiplication on a reconfigurable many-core architecture. DSD 2015, Euromicro Conference on Digital System Design. ISBN 978-1-4673-8035-5. pp. 330-336, 2015 978-1-4673-8035-5 http://hdl.handle.net/10400.21/6015 10.1109/DSD.2015.89 |
Idioma(s) |
eng |
Publicador |
IEEE-Institute Electrical Electronics Engineers INC |
Direitos |
closedAccess |
Palavras-Chave | #Sparse matrix #FPGA #Many-core #Matrix multiplication |
Tipo |
conferenceObject |