Towards printed carbon nanotube transistors on paper substrates

This thesis reports the work performed in the optimization of deposition parameters of Multi – Walled Carbon Nanotubes (MWCNT) targeting the development of a Field Effect Transistors (FET) on paper substrates. The CNTs were dispersed in a water solution with sodium dodecyl sulphate (SDS) through ultrasonication, ultrasonic bath and a centrifugation to remove the supernatant and have a homogeneous solution. Several deposition tests were performed using different types of CNTs, dis-persants, papers substrates and deposition techniques, such as spray coating and inkjet printing. The characterization of CNTs was made by Scanning Electron Microscopy (SEM) and Hall Effect. The most suitable CNT coatings able to be used as semiconductor in FETs were deposited by spray coat-ing on a paper substrate with hydrophilic nanoporous surface (FS2) at 100 ºC, 4 bar, 10 cm height, 5 second of deposition time and 90 seconds of drying between steps (4 layers of CNTs were deposited). Planar electrolyte gated FETs were produced with these layers using gold-nickel gate, source and drain electrodes. Despite the small current modulation (Ion/Ioff ratio of 1.8) one of these devices have p-type conduction with a field effect mobility of 1.07 cm2/V.s.

Field-effect transistors based on Zinc oxide nanoparticles

This work reports the development of field-effect transistors (FETs), whose channel is based on zinc oxide (ZnO) nanoparticles (NPs). Using screen-printing as the primary deposition technique, different inks were developed, where the semiconducting ink is based on a ZnO NPs dispersion in ethyl cellulose (EC). These inks were used to print electrolyte-gated transistors (EGTs) in a staggered-top gate structure on glass substrates, using a lithium-based polymeric electrolyte. In another approach, FETs with a staggered-bottom gate structure on paper were developed using a sol-gel method to functionalize the paper’s surface with ZnO NPs, using zinc acetate dihydrate (ZnC4H6O4·2H2O) and sodium hydroxide (NaOH) as precursors. In this case, the paper itself was used as dielectric. The various layers of the two devices were characterized using X-ray diffraction (XRD), scanning electron microscopy (SEM), Fourier Transform Infrared spectroscopy (FTIR), thermogravimetric and differential scanning calorimetric analyses (TG-DSC). Electrochemical impedance spectroscopy (EIS) was used in order to evaluate the electric double-layer (EDL) formation, in the case of the EGTs. The ZnO NPs EGTs present electrical modulation for annealing temperatures equal or superior to 300 ºC and in terms of electrical properties they showed On/Off ratios in the order of 103, saturation mobilities (μSat) of 1.49x10-1 cm2(Vs)-1 and transconductance (gm) of 10-5 S. On the other hand, the ZnO NPs FETs on paper exhibited On/Off ratios in the order of 102, μSat of 4.83x10- 3 cm2(Vs)-1and gm around 10-8 S.

Model analític de les característiques DC de transistors de doble porta

En aquest treball s’implementa un model analític de les característiques DC del MOSFET de doble porta (DG-MOSFET), basat en la solució de l’equació de Poisson i en la teoria de deriva-difussió[1]. El MOSFET de doble porta asimètric presenta una gran flexibilitat en el disseny de la tensió llindar i del corrent OFF. El model analític reprodueix les característiques DC del DG-MOSFET de canal llarg i és la base per construir models circuitals tipus SPICE.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Low temperature amorphous and nanocrystalline silicon thin film transistors deposited by Hot-Wire CVD on glass substrate

Amorphous and nanocrystalline silicon films obtained by Hot-Wire Chemical Vapor Deposition have been incorporated as active layers in n-type coplanar top gate thin film transistors deposited on glass substrates covered with SiO 2. Amorphous silicon devices exhibited mobility values of 1.3 cm 2 V - 1 s - 1, which are very high taking into account the amorphous nature of the material. Nanocrystalline transistors presented mobility values as high as 11.5 cm 2 V - 1 s - 1 and resulted in low threshold voltage shift (∼ 0.5 V).

Stability of hydrogenated nanocrystalline silicon thin-film transistors

Hydrogenated nanocrystalline silicon thin-films were obtained by catalytic chemical vapour deposition at low substrate temperatures (150°C) and high deposition rates (10 Å/s). These films, with crystalline fractions over 90%, were incorporated as the active layers of bottom-gate thin-film transistors. The initial field-effect mobilities of these devices were over 0.5 cm 2/V s and the threshold voltages lower than 4 V. In this work, we report on the enhanced stability of these devices under prolonged times of gate bias stress compared to amorphous silicon thin-film transistors. Hence, they are promising candidates to be considered in the future for applications such as flat-panel displays.

Electronic transport in low temperature nanocrystalline silicon thin-film transistors obtained by Hot-Wire CVD

Hydrogenated nanocrystalline silicon (nc-Si:H) obtained by hot-wire chemical vapour deposition (HWCVD) at low substrate temperature (150 °C) has been incorporated as the active layer in bottom-gate thin-film transistors (TFTs). These devices were electrically characterised by measuring in vacuum the output and transfer characteristics for different temperatures. The field-effect mobility showed a thermally activated behaviour which could be attributed to carrier trapping at the band tails, as in hydrogenated amorphous silicon (a-Si:H), and potential barriers for the electronic transport. Trapped charge at the interfaces of the columns, which are typical in nc-Si:H, would account for these barriers. By using the Levinson technique, the quality of the material at the column boundaries could be studied. Finally, these results were interpreted according to the particular microstructure of nc-Si:H.

Thin Film Transistors obtained by Hot-Wire CVD

Hydrogenated microcrystalline silicon films obtained at low temperature (150-280°C) by hot wire chemical vapour deposition at two different process pressures were measured by Raman spectroscopy, X-ray diffraction (XRD) spectroscopy and photothermal deflection spectroscopy (PDS). A crystalline fraction >90% with a subgap optical absortion 10 cm -1 at 0.8 eV were obtained in films deposited at growth rates >0.8 nm/s. These films were incorporated in n-channel thin film transistors and their electrical properties were measured. The saturation mobility was 0.72 ± 0.05 cm 2/ V s and the threshold voltage around 0.2 eV. The dependence of their conductance activation energies on gate voltages were related to the properties of the material.

Top-gate microcrystalline silicon TFTs processed at low temperature (<200ºC)

N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 °C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2-N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it=6.4×10 10 eV -1 cm -2. High field effect mobility, 25 cm 2/V s for electrons and 1.1 cm 2/V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously.

Field-Programmable Gate Array Card for Readout and Control of Cryoelectronics

The main goal of the present Master’s Thesis project was to create a field-programmable gate array (FPGA) based system for the control of single-electron transistors or other cryoelectronic devices. The FPGA and similar technologies are studied in the present work. The fixed and programmable logic are compared with each other. The main features and limitations of the hardware used in the project are investigated. The hardware and software connections of the device to the computer are shown in detail. The software development techniques for FPGA-based design are described. The steps of design for programmable logic are considered. Furthermore, the results of filters implemented in the software are illustrated.

Multiscale sensing of antibody - antigen interactions by organic transistors and single-molecule force spectroscopy

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

Dependence of Generation-Recombination Noise With Gate Voltage in FD SOI MOSFETs

A model for computing the generation-recombination noise due to traps within the semiconductor film of fully depleted silicon-on-insulator MOSFET transistors is presented. Dependence of the corner frequency of the Lorentzian spectra on the gate voltage is addressed in this paper, which is different to the constant behavior expected for bulk transistors. The shift in the corner frequency makes the characterization process easier. It helps to identify the energy position, capture cross sections, and densities of the traps. This characterization task is carried out considering noise measurements of two different candidate structures for single-transistor dynamic random access memory devices.

In situ real-time investigation of Organic Ultra-Thin-Film transistors: growth, electrical properties and biosensing applications

Organic electronics has grown enormously during the last decades driven by the encouraging results and the potentiality of these materials for allowing innovative applications, such as flexible-large-area displays, low-cost printable circuits, plastic solar cells and lab-on-a-chip devices. Moreover, their possible field of applications reaches from medicine, biotechnology, process control and environmental monitoring to defense and security requirements. However, a large number of questions regarding the mechanism of device operation remain unanswered. Along the most significant is the charge carrier transport in organic semiconductors, which is not yet well understood. Other example is the correlation between the morphology and the electrical response. Even if it is recognized that growth mode plays a crucial role into the performance of devices, it has not been exhaustively investigated. The main goal of this thesis was the finding of a correlation between growth modes, electrical properties and morphology in organic thin-film transistors (OTFTs). In order to study the thickness dependence of electrical performance in organic ultra-thin-film transistors, we have designed and developed a home-built experimental setup for performing real-time electrical monitoring and post-growth in situ electrical characterization techniques. We have grown pentacene TFTs under high vacuum conditions, varying systematically the deposition rate at a fixed room temperature. The drain source current IDS and the gate source current IGS were monitored in real-time; while a complete post-growth in situ electrical characterization was carried out. At the end, an ex situ morphological investigation was performed by using the atomic force microscope (AFM). In this work, we present the correlation for pentacene TFTs between growth conditions, Debye length and morphology (through the correlation length parameter). We have demonstrated that there is a layered charge carriers distribution, which is strongly dependent of the growth mode (i.e. rate deposition for a fixed temperature), leading to a variation of the conduction channel from 2 to 7 monolayers (MLs). We conciliate earlier reported results that were apparently contradictory. Our results made evident the necessity of reconsidering the concept of Debye length in a layered low-dimensional device. Additionally, we introduce by the first time a breakthrough technique. This technique makes evident the percolation of the first MLs on pentacene TFTs by monitoring the IGS in real-time, correlating morphological phenomena with the device electrical response. The present thesis is organized in the following five chapters. Chapter 1 makes an introduction to the organic electronics, illustrating the operation principle of TFTs. Chapter 2 presents the organic growth from theoretical and experimental points of view. The second part of this chapter presents the electrical characterization of OTFTs and the typical performance of pentacene devices is shown. In addition, we introduce a correcting technique for the reconstruction of measurements hampered by leakage current. In chapter 3, we describe in details the design and operation of our innovative home-built experimental setup for performing real-time and in situ electrical measurements. Some preliminary results and the breakthrough technique for correlating morphological and electrical changes are presented. Chapter 4 meets the most important results obtained in real-time and in situ conditions, which correlate growth conditions, electrical properties and morphology of pentacene TFTs. In chapter 5 we describe applicative experiments where the electrical performance of pentacene TFTs has been investigated in ambient conditions, in contact to water or aqueous solutions and, finally, in the detection of DNA concentration as label-free sensor, within the biosensing framework.

Transistors elettrochimici organici e la loro applicazione come sensori.

La presente tesi tratta della fabbricazione e del funzionamento di transistors elettrochimici organici (OECTs) composti da fi�lm sottili di poly(3,4-ethylenedioxythiophene) disperso con polystyrenesulfonic acid, o PEDOT:PSS, oltre che del loro possibile utilizzo come sensori. La trattazione si apre con una panoramica sui polimeri conduttivi, siano essi puri o drogati, e sulle loro caratteristiche chimiche ed elettriche: diversi metodi di drogaggio consentono il loro utilizzo come semiconduttori. Tra questi polimeri, il PEDOT �e uno dei pi�u utilizzati poich�e presenta accessibilit�a d'uso e ottima stabilit�a nel suo stato drogato, pur risultando insolubile in acqua; per ovviare a questo problema lo si polimerizza con PSS. Le propriet�a di questo composto sono poi ampiamente discusse, soprattutto in ambito di applicazioni tecniche, per le quali �e neccessario che il polimero in soluzione sia depositato su un substrato. A questo scopo vengono presentate le principali techiche che consentono la deposizione, permettendo di creare fil�lm sottili di materiale da utilizzarsi, nell'ambito di questa tesi, come gate e canale dei transistors elettrochimici. A seguire viene esposta la struttura degli OECTs e spiegato il loro funzionamento, modellizzando i dispositivi con un semplice circuito elettrico. Il confronto dei meno noti OECTs con i meglio conosciuti transistors a eff�etto campo semplifi�ca la comprensione del funzionamento dei primi, i quali sono rilevanti ai fi�ni di questa trattazione per il loro possibile funzionamento come sensori. In seguito alla spiegazione teorica, vengono illustrati i metodi seguiti per la deposizione di �film sottili di PEDOT:PSS tramite Spin Coating e per la fabbricazione degli OECTs su cui sono state eff�ettuate le misure, le quali sono state scelte e presentate in base ai risultati gi�a ottenuti in letteratura e a seconda dei dati ritenuti necessari alla caratterizzazione del transistor elettrochimico nell'ottica di un suo possibile utilizzo come sensore. Perci�o sono state eseguite misure amperometriche in funzione delle tensioni di gate e di drain, alternatamente tenendo costante una e variando l'altra, oltre che in funzione della concentrazione di elettrolita, dell'area del canale e del tempo. In conclusione sono presentati i dati sperimentali ottenuti ed una loro analisi.