Conduction-electron localized-moment interaction in palladium-silicon base amorphous alloys containing transition metals

The electrical and magnetic properties of amorphous alloys obtained by rapid quenching from the liquid state have been studied. The composition of these alloys corresponds to the general formula M_xPd_80-xSi₂₀, in which M stands for a metal of the first transition series between chromium and nickel and x is its atomic concentration. The concentration ranges within which an amorphous structure could be obtained were: from 0 to 7 for Cr, Mn and Fe, from 0 to 11 for Co and from 0 to 15 for Ni. A well-defined minimum in the resistivity vs temperature curve was observed for all alloys except those containing nickel. The alloys for which a resistivity minimum was observed had a negative magnetoresistivity approximately proportional to the square of the magnetization and their susceptibility obeyed the Curie-Weiss law in a wide temperature range. For concentrated Fe and Co alloys the resistivity minimum was found to coexist with ferromagnetism. These observations lead to the conclusion that the present results are due to a s-d exchange interaction. The unusually high resistivity minimum temperature observed in the Cr alloys is interpreted as a result of a high Kondo temperature and a large s-d exchange integral. A low Fermi energy of the amorphous alloys (3.5 eV) is also responsible for the anomalies due to the s-d exchange interaction.

Optical properties of excited silicon and germanium at low temperatures

Part I of this thesis deals with 3 topics concerning the luminescence from bound multi-exciton complexes in Si. Part II presents a model for the decay of electron-hole droplets in pure and doped Ge.

Part I.

We present high resolution photoluminescence data for Si doped With Al, Ga, and In. We observe emission lines due to recombination of electron-hole pairs in bound excitons and satellite lines which have been interpreted in terms of complexes of several excitons bound to an impurity. The bound exciton luminescence in Si:Ga and Si:Al consists of three emission lines due to transitions from the ground state and two low lying excited states. In Si:Ga, we observe a second triplet of emission lines which precisely mirror the triplet due to the bound exciton. This second triplet is interpreted as due to decay of a two exciton complex into the bound exciton. The observation of the second complete triplet in Si:Ga conclusively demonstrates that more than one exciton will bind to an impurity. Similar results are found for Si:Al. The energy of the lines show that the second exciton is less tightly bound than the first in Si:Ga. Other lines are observed at lower energies. The assumption of ground state to ground-state transitions for the lower energy lines is shown to produce a complicated dependence of binding energy of the last exciton on the number of excitons in a complex. No line attributable to the decay of a two exciton complex is observed in Si:In.

We present measurements of the bound exciton lifetimes for the four common acceptors in Si and for the first two bound multi-exciton complexes in Si:Ga and Si:Al. These results are shown to be in agreement with a calculation by Osbourn and Smith of Auger transition rates for acceptor bound excitons in Si. Kinetics determine the relative populations of complexes of various sizes and work functions, at temperatures which do not allow them to thermalize with respect to one another. It is shown that kinetic limitations may make it impossible to form two-exciton complexes in Si:In from a gas of free excitons.

We present direct thermodynamic measurements of the work functions of bound multi-exciton complexes in Al, B, P and Li doped Si. We find that in general the work functions are smaller than previously believed. These data remove one obstacle to the bound multi-exciton complex picture which has been the need to explain the very large apparent work functions for the larger complexes obtained by assuming that some of the observed lines are ground-state to ground-state transitions. None of the measured work functions exceed that of the electron-hole liquid.

Part II.

A new model for the decay of electron-hole-droplets in Ge is presented. The model is based on the existence of a cloud of droplets within the crystal and incorporates exciton flow among the drops in the cloud and the diffusion of excitons away from the cloud. It is able to fit the experimental luminescence decays for pure Ge at different temperatures and pump powers while retaining physically reasonable parameters for the drops. It predicts the shrinkage of the cloud at higher temperatures which has been verified by spatially and temporally resolved infrared absorption experiments. The model also accounts for the nearly exponential decay of electron-hole-droplets in lightly doped Ge at higher temperatures.

Taper-free and kinked germanium nanowires grown on silicon via purging and the two-temperature process

We investigate the growth procedures for achieving taper-free and kinked germanium nanowires epitaxially grown on silicon substrates by chemical vapor deposition. Singly and multiply kinked germanium nanowires consisting of 111 segments were formed by employing a reactant gas purging process. Unlike non-epitaxial kinked nanowires, a two-temperature process is necessary to maintain the taper-free nature of segments in our kinked germanium nanowires on silicon. As an application, nanobridges formed between (111) side walls of V-grooved (100) silicon substrates have been demonstrated. © 2012 IOP Publishing Ltd.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

STRUCTURAL DEFECTS AND THEIR ELECTRICAL-ACTIVITY IN GERMANIUM IMPLANTED SILICON

The electrical and structural characteristics of secondary defects in regrown amorphous layers formed in n-type Si(100) with a resistivity of 2 OMEGA cm and 6 OMEGA cm using Ge+ ions, has been studied. The amorphous layers with a thickness of 460 nm are formed by implantation of 1 x 10(15) Ge+ cm-2 at an energy of 400 keV. Both conventional furnace and rapid thermal annealing were used to regrow the amorphous layer and the residual defects have been characterised in terms of their concentration depth distribution and activation energies using C-V and DLTS. Structural information has been obtained from RBS and XTEM. By choosing suitable anneal conditions it is possible to eliminate extended defects, apart from a low concentration of end of range dislocation loops. However, a substantial population of electrically active point defects remain after simple low thermal budget anneals. In a sample implanted with 1 x 10(15) Ge+ cm-2 at 400 keV a region of deep donors approximately 460 nm from the surface is always present When the samples are annealed at higher temperatures (> 850-degrees the total deep donor concentration is reduced by one order of magnitude. Other electrically active defects not observable in the low (750-degrees-C) temperature annealed layers become apparent during anneals at intermediate temperatures.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Nanosize effect in germanium nanowire growth with binary metal alloys

This article describes feasible and improved ways towards enhanced nanowire growth kinetics by reducing the equilibrium solute concentration in the liquid collector phase in a vapor-liquid-solid (VLS) like growth model. Use of bi-metallic alloy seeds (AuxAg1-x) influences the germanium supersaturation for a faster nucleation and growth kinetics. Nanowire growth with ternary eutectic alloys shows Gibbs-Thompson effect with diameter dependent growth rate. In-situ transmission electron microscopy (TEM) annealing experiments directly confirms the role of equilibrium concentration in nanowire growth kinetics and was used to correlate the equilibrium content of metastable alloys with the growth kinetics of Ge nanowires. The shape and geometry of the heterogeneous interfaces between the liquid eutectic and solid Ge nanowires were found to vary as a function of nanowire diameter and eutectic alloy composition.

Germanium MOS Capacitors with Hafnium Dioxide and Silicon Dioxide Dielectrics

Germanium (Ge) does not grow a suitable oxide for MOS devices. The Ge/dielectric interface is of prime importance to the operation of photo-detectors and scaled MOSTs. Therefore there is a requirement for deposited or bonded dielectric materials. MOS capacitors have been formed on germanium substrates with three different dielectric materials. Firstly, a thermally grown and bonded silicon dioxide (SiO2) layer, secondly, SiO2 deposited by atmospheric pressure CVD ‘silox’, and thirdly a hafnium oxide (HfO2) high-k dielectric deposited by atomic layer deposition (ALD). Ge wafers used were p-type 1 0 0 2 O cm. C–V measurements have been made on all three types of capacitors to assess the interface quality. ALD HfO2 and silox both display acceptable C–V characteristics. Threshold voltage and maximum and minimum capacitance values closely match expected values found through calculation. However, the bonded SiO2 has non-ideal C–V characteristics, revealing the presence of a high density of interface states. A H2/N2 post metal anneal has a detrimental effect on C–V characteristics of HfO2 and silox dielectrics, causing a shift in the threshold voltage and rise in the minimum capacitance value. In the case of hafnium dioxide, capacitor properties can be improved by performing a plasma nitridation of the Ge surface prior to dielectric deposition.

Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates

Hafnium oxide films have been deposited at 250 °C on silicon and germanium substrates by atomic layer deposition (ALD), using tetrakis-ethylmethylamino hafnium (TEMAH) and water vapour as precursors in a modified Oxford Instruments PECVD system. Self-limiting monolayer growth has been verified, characterised by a growth rate of 0.082 nm/ cycle. Layer uniformity is approximately within ±1% of the mean value. MOS capacitors have been fabricated by evaporating aluminium electrodes. CV analysis has been used to determine the bulk and interface properties of the HfO 2, and their dependence on pre-clean schedule, deposition conditions and post-deposition annealing. The dielectric constant of the HfO 2 is typically 18. On silicon, best results are obtained when the HfO 2 is deposited on a chemically oxidised hydrophilic surface. On germanium, best results are obtained when the substrate is nitrided before HfO 2 deposition, using an in-situ nitrogen plasma treatment. © Springer Science+Business Media, LLC 2007.