A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.

Modeling and Analysis of Noise Margin in SET Logic

In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH, etc.) and noise margin. Finally the noise immunity of SET logic is compared with current CMOS logic.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantizationmainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as ``quantization threshold'') that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studiedfor the current-biased negative differential resistance (NDR) circuitand hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.

Intrinsic limits of subthreshold slope in biased bilayer graphene transistor

In this work, we investigate the intrinsic limits of subthreshold slope in a dual gated bilayer graphene transistor using a coupled self-consistent Poisson-bandstructure solver. We benchmark the solver by matching the bias dependent band gap results obtained from the solver against published experimental data. We show that the intrinsic bias dependence of the electronic structure and the self-consistent electrostatics limit the subthreshold slope obtained in such a transistor well above the Boltzmann limit of 60 mV/decade at room temperature, but much below the results experimentally shown till date, indicating room for technological improvement of bilayer graphene.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 mu m x 5 mu m shows a single 2D band at 2687 cm(-1), characteristic of single-layer graphene.The two-probe current-voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 mu m using ac dielectrophoresis, show ohmic behavior with a resistance of similar to 37 k Omega. The temperature dependence of the resistance (R) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [dR/dT]/R similar to -9.5 x 10(-4)/K, the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO + LiClO4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of similar to 6 x 10(12)/cm(2) and carrier mobility of similar to 50 cm(2)/V s. The source-drain current characteristics show a tendency of current saturation at high source-drain voltage which is analyzed quantitatively by a diffusive transport model. (C) 2010 Elsevier Ltd. All rights reserved.

Interfaces and traps in pentacene field-effect transistor

The equivalent circuit parameters for a pentacene organic field-effect transistor are determined from low frequency impedance measurements in the dark as well as under light illumination. The source-drain channel impedance parameters are obtained from Bode plot analysis and the deviations at low frequency are mainly due to the contact impedance. The charge accumulation at organic semiconductor-metal interface and dielectric-semiconductor interface is monitored from the response to light as an additional parameter to find out the contributions arising from photovoltaic and photoconductive effects. The shift in threshold voltage is due to the accumulation of photogenerated carriers under source-drain electrodes and at dielectric-semiconductor interface, and also this dominates the carrier transport. The charge carrier trapping at various interfaces and in the semiconductor is estimated from the dc and ac impedance measurements under illumination. (c) 2010 American Institute of Physics. doi: 10.1063/1.3517085]

Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor

In this paper, a physically based analytical quantum linear threshold voltage model for short channel quad gate MOSFETs is developed. The proposed model, which is suitable for circuit simulation, is based on the analytical solution of 3-D Poisson and 2-D Schrodinger equation. Proposed model is fully validated against the professional numerical device simulator for a wide range of device geometries and also used to analyze the effect of geometry variation on the threshold voltage.

Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS

We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.