Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs


Autoria(s): Harish, BP; Bhat, Navakanta; Patil, Mahesh B
Data(s)

2007

Resumo

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/26814/1/process.pdf

Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2007) Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs. In: International Conference on Computing - Theory and Applications (ICCTA 2007), MAR 05-07, 2007, Calcutta.

Publicador

IEEE

Relação

http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=4127349&queryText%3DProcess+variability-aware+statistical++hybrid+modeling++of+dynamic+power++dissipation+in+65++nm+CMOS+designs%26openedRefinements%3D*%26searchField%3DSearch+All

http://eprints.iisc.ernet.in/26814/

Palavras-Chave #Electrical Communication Engineering
Tipo

Conference Paper

PeerReviewed