A high-performance Si-based MOS electrooptic phase modulator with a shunt-capacitor configuration

A novel Si-based metal-oxide-semiconductor (MOS) electrooptic phase modulator including two shunt oxide layer capacitors integrated on a silicon-on-insulator (SOI) waveguide is simulated and analyzed. The refractive index near the two gate oxide layers is modified by the free carrier dispersion effect induced by applying a positive bias on the electrodes. The theoretical calculation of free carrier distribution coupled with optical guided mode propagation characteristics has been carried out. The influence of the structure parameters such as the width and the doping level of the active region are analyzed. A half-wave voltage V-pi = 4 V is demonstrated with an 8-mm active region length and a 4-mu m width of an inner rib under an accumulation mode. When decreasing the inner rib width to 1 mu m, the phase modulation efficiency is even higher, and the rise and fall times reach 50 and 40 ps, respectively, with a 1.0 x 10(17) cm(-3) doping level in the active region.

Size tolerance analysis of a 4X4 tapered multimode interference coupler in a silicon-on-insulator structure

Size tolerance of a 4X4 general interference tapered multimode interference (MMI) coupler in a silicon-on-insulator (SOI) structure is investigated by means of a 2-D finite difference beam propagation method (2D-FDBPM), together with an effective refractive index method (EIM). The results show that the tapered multimode interference coupler exhibits relatively larger size tolerance when light is launched from the edgeport than from midport, though it has much better output power uniformity when light is launched from midport. Besides that, it can reduce the device length greatly. The 4X4 general interference tapered MMI coupler has a slightly larger size tolerance compared with a conventional straight multimode interference coupler. (C) 2003 Society of Photo-Optical Instrumentation Engineers.

Improving response speed of electrooptical switch in silicon-on-insulator by modifying modulation area structure

This paper reports on the simulation of two 2 x 2 electrooptical switches with different modulation area structures in silicon-on-insulator (SOI). A two-dimensional (2D) semiconductor device simulation tool PISCES-II has been used to analyze the dc and transient behaviors of the two devices. The modeling results show that the switch with an N+-I-P+-I-N+ modulation structure has a much faster response speed than the device with a P+-I-N+ modulation structure, although the former requires slightly stronger injection power.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Fabrication of novel double-hetero-epitaxial SOT structure Si/gamma-Al2O3/Si

In this paper, we report the fabrication of Si-based double-hetero-epitaxial silicon on insulator (SOI) structure Si/gamma-Al2O3/Si. Firstly, single crystalline gamma-Al2O3(100) insulator films were grown epitaxially on Si(100) using the sources of TMA (Al(CH3)(3)) and O-2 by very low-pressure chemical vapor deposition. Afterwards, Si(100) epitaxial films were grown on gamma-Al2O3 (100)/Si(100) epi-substrates using a chemical vapor deposition method similar to the silicon on sapphire epitaxial growth. The Si/gamma-Al2O3/Si SOL materials are characterized in detail by reflect high-energy electron diffraction, X-ray diffraction and Auger energy spectrum (AES) techniques. The insulator layer of gamma-Al2O3 has an excellent dielectric property. The leakage current is less than 1 x 10(-10) A/cm(2) when the electric field is below 1.3 MV/ cm. The Si film grown on gamma-Al2O3/Si epi-substrates was single crystalline. Meanwhile, the AES depth profile of the SOL structure shows that the composition of gamma-Al2O3 film is uniform, and the carbon contamination is not observed. Additionally, the gamma-Al2O3/Si epi-substrates are suitable candidates as a platform for a variety of active layers such as GaN, SiC and GeSi. It shows a bright future for microelectronic and optical electronics applications. (C) 2002 Elsevier Science B.V. All rights reserved.

Fabrication of 4 x 4 tapered MMI coupler with large cross section

MMI coupler with large cross section has low coupling loss between the device and fiber. However, large chip area is required. Recently proposed N x N tapered MMI coupler shows a substantial reduction in device geometry. No such kind of devices with N > 2 has yet been realized up to now. The authors have demonstrated a 4 x 4 parabolically tapered MMI coupler with large cross section that can match the SM fiber in silicon-on-insulator (SOI) technology. The device exhibits a minimum uniformity of 0.36 dB and excess loss of 3.7 dB, It represents a key component for realization of MMI-based silicon integrated optical circuit technology.

The new exploration for proton-implanted silicon: the conversion of a surface-region-purification-induced p-n junction into a p-i-n electrical structure approaching silicon on insulator

A surface-region-purification-induced p-n junction, a puzzle discovered at Brookhaven National Laboratory, in a silicon-on-defect-layer (SODL) material has been explored by carrying out various annealing conditions and subsequent measurements on electrical properties. The origin of the pn junction has been experimentally investigated. Furthermore, the p-n junction has been transformed into a p-i-n electrical structure by adding a high temperature annealing process to the previously used SODL procedure, making the SODL material approach silicon on insulator (SOI). The control of the initial oxygen amount in the silicon material is suggested to be critical for the experimental results.

中国材料工程大典—信息功能材料工程

本书是《中国材料工程大典》中的卷目之一。 信息功能材料是信息科学技术和信息产业发展的基础和先导。21世纪将是以信息产业为核心的知识经济时代，对信息技术和信息资源的竞争将更加激烈。我国电子信息行业2004年完成产品销售收入达26500亿元，多年来已居外贸出口首位，并继续以高出工业发展速度10％的速度发展，已成为世界信息产业大国。加快由信息产业大国向信息产业强国迈进的步伐，是我们广大从事信息技术，特别是信息功能材料工作者义不容辞的责任。希望《中国材料工程大典》中《信息功能材料工程》卷的出版，将有力推动我国信息技术和信息产业的健康发展。 《信息功能材料工程》分上、中、下卷，共设20篇，约600万字。它涉及到信息的获取、传输、存储、显示和处理等主要技术用的材料与器件，是目前我国该领域比较完整的专业工具书。参加这部书编写的有中科院、高校和部分企业的专家教授近200名。参加编写的主要单位有中科院半导体研究所、中科院物理研究所、中科院微电子研究所、中科院上海精密光学机械研究所、中科院上海红外技术物理研究所、中科院长春应用化学研究所、中科院合肥固体物理所、南京大学、清华大学、西安理工大学、北京有色金属研究总院、武汉邮电科学研究院等。历时近3年完稿。由王占国、陈立泉、屠海令任主编并统稿。 本卷各篇不仅全面系统地反映了国外信息功能材料研究领域的现状、最新进展和发展趋势，而且也特别注重我国在该领域的研发和产业化方面取得的成果，力图使其具有实用性、先进性和权威性。本书适合于从事信息功能材料的科研工作者和工程技术人员查阅使用，也可供有关师生参考。

微电子与光电子集成技术

微电子技术与光电子技术紧密结合，相互渗透，必将推进信息技术及相关的高新技术进入新的发展阶段。本书共分为9章，从技术基础和实际应用的角度出发，着重对微电子与光电子集成技术相关的工艺基础、基本原理和关键集成技术进行了详细阐述，主要内容包括光发射器件、光电探测器、光波导器件、光电子专用集成电路、硅基光电子集成回路、甚短距离光传输技术以及微电子与光电子混合集成技术等。 微电子与光电子集成技术的实用化进程，必将为21世纪科学技术的发展作出重大贡献。然而，微电子与光电子集成技术是信息技术发展的一个崭新方向，虽然各项关键技术的发展取得了一定的进步，但还存在诸多难题需要进一步解决和完善。 本书主要为从事集成光电子和光通信等相关技术研究的科研人员提供参考。

High efficiency fiber to waveguide optical coupler in silicon-on-insulator-based slot waveguides - art. no. 68310R

We propose a novel optical fiber-to-waveguide coupler for integrated optical circuits. The proper materials and structural parameters of the coupler, which is based on a slot waveguide, are carefully analyzed using a full-vectorial three dimensional mode solver. Because the effective refractive index of the mode in a silicon-on-insulator-based slot waveguide can be extremely close to that of the fiber, a highly efficient fiber-to-waveguide coupling application can be realized. For a TE-like mode, the calculated minimum mismatch loss is about 1.8dB at 1550nm, and the mode conversion loss can be less than 0.5dB. The discussion of the present state-of-the-art is also involved. The proposed coupler can be used in chip-to-chip communication.

Design considerations for a silicon-based p-i-n phase modulator in a double ridge waveguide with side isolating grooves

We present detail design considerations and simulation results of a forward biased carrier injection p-i-n modulator integrated on SOI rib waveguides. To minimize the free carrier absorption loss while keeping the comparatively small lateral dimensions of the modulator as required for high speed operation, we proposed two structural improvements, namely the double ridge (terrace ridge) structure and the isolating grooves at both sides of the double ridge. With improved carrier injection and optical confinement structure, the simulated modulator response time is in sub-ns range and absorption loss is minimized.

Fabrication of improved FD SOIMOSFETs for suppressing edge effect

FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to reduce the edge effect and qualified devices are fabricated successfully.

Design and Fabrication of a Photonic Crystal Channel Drop Filter Based on an Asymmetric Silicon-on-Insulator Slab

We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.

Fabrication method of silicon nanostructures by anisotropic etching

A fabrication method of silicon nanostructures is presented. Silicon nanowire, shift-line structure and islands have been successfully fabricated on SOI wafer using e-beam lithography and anisotropic etching technique.

Si-based membrane resonant cavity enhanced photodetectors

Si-based membrane RCE photodetectors were introduced. The RCE photodiodes were fabricated on silicon membranes formed from SOI substrate. Compared with the conventional p-i-n photodiode, the responsivity has a threefold enhancement.