An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

A Low Power Wide Dynamic Range Envelope Detector

We report a 75dB, 2.8mW, 100Hz-10kHz envelope detector in a 1.5mm 2.8V CMOS technology. The envelope detector performs input-dc-insensitive voltage-to-currentconverting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide- linear-range transconductor (WLR OTA) allows greater than 1.7Vpp input voltage swings. We show theoretically that this optimal performance is technology-independent for the given topology and may be improved only by spending more power. A novel circuit topology is used to perform 140nW peak detection with controllable attack and release time constants. The lower limits of envelope detection are determined by the more dominant of two effects: The first effect is caused by the inability of amplified high-frequency signals to exceed the deadzone created by exponential nonlinearities in the rectifier. The second effect is due to an output current caused by thermal noise rectification. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low power bionic implants for the deaf, hearing aids, and speech-recognition front ends. Extension of the envelope detector to higher- frequency applications is straightforward if power consumption is inc

Performance evaluation of the RPL Protocol in fixed and mobile sinks low-power and lossy networks.

Low-Power and Lossy-Network (LLN) are usually composed of static nodes, but the increase demand for mobility in mobile robotic and dynamic environment raises the question how a routing protocol for low-power and lossy-networks such as (RPL) would perform if a mobile sink is deployed. In this paper we investigate and evaluate the behaviour of the RPL protocol in fixed and mobile sink environments with respect to different network metrics such as latency, packet delivery ratio (PDR) and energy consumption. Extensive simulation using instant Contiki simulator show significant performance differences between fixed and mobile sink environments. Fixed sink LLNs performed better in terms of average power consumption, latency and packet delivery ratio. The results demonstrated also that RPL protocol is sensitive to mobility and it increases the number of isolated nodes.

Practical wireless sensor networks power consumption metrics for building energy management applications

The power consumption of wireless sensor networks (WSN) module is an important practical concern in building energy management (BEM) system deployments. A set of metrics are created to assess the power profiles of WSN in real world condition. The aim of this work is to understand and eventually eliminate the uncertainties in WSN power consumption during long term deployments and the compatibility with existing and emerging energy harvesting technologies. This paper investigates the key metrics in data processing, wireless data transmission, data sensing and duty cycle parameter to understand the system power profile from a practical deployment prospective. Based on the proposed analysis, the impacts of individual metric on power consumption in a typical BEM application are presented and the subsequent low power solutions are investigated.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

An optimal algorithm for low power multiplierless FIR filter design using chebychev criterion

In this paper, we propose a novel finite impulse response (FIR) filter design methodology that reduces the number of operations with a motivation to reduce power consumption and enhance performance. The novelty of our approach lies in the generation of filter coefficients such that they conform to a given low-power architecture, while meeting the given filter specifications. The proposed algorithm is formulated as a mixed integer linear programming problem that minimizes chebychev error and synthesizes coefficients which consist of pre-specified alphabets. The new modified coefficients can be used for low-power VLSI implementation of vector scaling operations such as FIR filtering using computation sharing multiplier (CSHM). Simulations in 0.25um technology show that CSHM FIR filter architecture can result in 55% power and 34% speed improvement compared to carry save multiplier (CSAM) based filters.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Inexact-aware architecture design for ultra-low power bio-signal analysis

This study introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimise energy consumption. In this scenario, the reliability of static RAM (SRAM) memories cannot be guaranteed when using conventional 6-transistor implementations. While error correction codes and dedicated SRAM implementations can ensure correct operations in this near-threshold regime, they incur in significant area and energy overheads, and should therefore be employed judiciously. Herein, the authors propose a novel scheme to design inexact computing architectures that selectively protects memory regions based on their significance, i.e. their impact on the end-to-end quality of service, as dictated by the bio-signal application characteristics. The authors illustrate their scheme on an industrial benchmark application performing the power spectrum analysis of electrocardiograms. Experimental evidence showcases that a significance-based memory protection approach leads to a small degradation in the output quality with respect to an exact implementation, while resulting in substantial energy gains, both in the memory and the processing subsystem.

Reference clock design for low power and low phase noise with temperature compensation

Thesis (Ph.D.)--University of Washington, 2016-03

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).