Controlo de conversores de potência genéricos por FPGA

Dissertação para obtenção do grau de Mestre em Engenharia Eletrotécnica Ramo de Automação e Eletrónica Industrial

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e Tecnologia

Pipelined analog-to-digital conversion using current-mode reference shifting

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Diffusion spectrum imaging shows the structural basis of functional cerebellar circuits in the human cerebellum in vivo.

BACKGROUND: The cerebellum is a complex structure that can be affected by several congenital and acquired diseases leading to alteration of its function and neuronal circuits. Identifying the structural bases of cerebellar neuronal networks in humans in vivo may provide biomarkers for diagnosis and management of cerebellar diseases. OBJECTIVES: To define the anatomy of intrinsic and extrinsic cerebellar circuits using high-angular resolution diffusion spectrum imaging (DSI). METHODS: We acquired high-resolution structural MRI and DSI of the cerebellum in four healthy female subjects at 3T. DSI tractography based on a streamline algorithm was performed to identify the circuits connecting the cerebellar cortex with the deep cerebellar nuclei, selected brainstem nuclei, and the thalamus. RESULTS: Using in-vivo DSI in humans we were able to demonstrate the structure of the following cerebellar neuronal circuits: (1) connections of the inferior olivary nucleus with the cerebellar cortex, and with the deep cerebellar nuclei (2) connections between the cerebellar cortex and the deep cerebellar nuclei, (3) connections of the deep cerebellar nuclei conveyed in the superior (SCP), middle (MCP) and inferior (ICP) cerebellar peduncles, (4) complex intersections of fibers in the SCP, MCP and ICP, and (5) connections between the deep cerebellar nuclei and the red nucleus and the thalamus. CONCLUSION: For the first time, we show that DSI tractography in humans in vivo is capable of revealing the structural bases of complex cerebellar networks. DSI thus appears to be a promising imaging method for characterizing anatomical disruptions that occur in cerebellar diseases, and for monitoring response to therapeutic interventions.

Brain tissue properties differentiate between motor and limbic basal ganglia circuits.

Despite advances in understanding basic organizational principles of the human basal ganglia, accurate in vivo assessment of their anatomical properties is essential to improve early diagnosis in disorders with corticosubcortical pathology and optimize target planning in deep brain stimulation. Main goal of this study was the detailed topological characterization of limbic, associative, and motor subdivisions of the subthalamic nucleus (STN) in relation to corresponding corticosubcortical circuits. To this aim, we used magnetic resonance imaging and investigated independently anatomical connectivity via white matter tracts next to brain tissue properties. On the basis of probabilistic diffusion tractography we identified STN subregions with predominantly motor, associative, and limbic connectivity. We then computed for each of the nonoverlapping STN subregions the covariance between local brain tissue properties and the rest of the brain using high-resolution maps of magnetization transfer (MT) saturation and longitudinal (R1) and transverse relaxation rate (R2*). The demonstrated spatial distribution pattern of covariance between brain tissue properties linked to myelin (R1 and MT) and iron (R2*) content clearly segregates between motor and limbic basal ganglia circuits. We interpret the demonstrated covariance pattern as evidence for shared tissue properties within a functional circuit, which is closely linked to its function. Our findings open new possibilities for investigation of changes in the established covariance pattern aiming at accurate diagnosis of basal ganglia disorders and prediction of treatment outcome.

Analog circuit for real-time computation of respiratory mechanical impedance in sleep studies

The aim of this work was to develop a low-cost circuit for real-time analog computation of the respiratory mechanical impedance in sleep studies. The practical performance of the circuit was tested in six patients with obstructive sleep apnea. The impedance signal provided by the analog circuit was compared with the impedance calculated simultaneously with a conventional computerized system. We concluded that the low-cost analog circuit developed could be a useful tool for facilitating the real-time assessment of airway obstruction in routine sleep studies.

Analog circuit for real-time computation of respiratory mechanical impedance in sleep studies

The aim of this work was to develop a low-cost circuit for real-time analog computation of the respiratory mechanical impedance in sleep studies. The practical performance of the circuit was tested in six patients with obstructive sleep apnea. The impedance signal provided by the analog circuit was compared with the impedance calculated simultaneously with a conventional computerized system. We concluded that the low-cost analog circuit developed could be a useful tool for facilitating the real-time assessment of airway obstruction in routine sleep studies.

A current-mode based Field-Programmable Analog Array for signal processing applications

This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.

Low voltage analog synthesizer of orthogonal signals: A current-mode approach

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Experimental results using 0.35 mu m AMS CMOS process are presented for generation of the cosine and Legendre basis.

An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.

Low voltage analog synthesizer of orthogonal signals using current mode techniques

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Simulation results using 0.35 mu m AMS CMOS process are presented for generation of the cosine and Legendre basis.

A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

On optimizing micropower MOS regulated cascode circuits on switched current techniques

Trade-off between settling time and micropower consumption in MOS regulated cascode current sources as building parts in high-accuracy, current-switching D/A converters is analyzed. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are discussed. Raising pole frequencies while meeting consumption requirements is basically limited by parasitic capacitances. An alternative is found by imposing a twin-pole system in which design constraints are somewhat relaxed and settling slightly faster. Relationships between pole frequencies, transistor geometry and bias are established. Simulated waveforms obtained with PSpice of designed circuits following a voltage perturbation suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves its simulated settling performance.

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

An analog implementation of radial basis neural networks (RBNN) using BiCMOS technology

This paper describes a analog implementation of radial basis neural networks (RBNN) in BiCMOS technology. The RBNN uses a gaussian function obtained through the characteristic of the bipolar differential pair. The gaussian parameters (gain, center and width) is changed with programmable current source. Results obtained with PSPICE software is showed.