An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
Contribuinte(s) |
Universidade Estadual Paulista (UNESP) |
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Data(s) |
20/05/2014
20/05/2014
01/01/1999
|
Resumo |
In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz. |
Formato |
520-521 |
Identificador |
http://dx.doi.org/10.1109/MWSCAS.1998.759544 1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 520-521, 1999. http://hdl.handle.net/11449/9725 10.1109/MWSCAS.1998.759544 WOS:000079563200120 |
Idioma(s) |
eng |
Publicador |
IEEE Computer Soc |
Relação |
1998 Midwest Symposium on Circuits and Systems, Proceedings |
Direitos |
closedAccess |
Tipo |
info:eu-repo/semantics/conferencePaper |