Blurring the physical boundaries of the city: Media architecture and urban informatics for community engagement

Architecture focuses on designing built environments in response to society’s needs, reflecting culture through materials and forms. The physical boundaries of the city have become blurred through the integration of digital media, connecting the physical environment with the digital. In the recent past the future was imagined as highly technological; 1982 Ridley Scott’s Blade Runner is set in 2019 and introduces a world where supersized screens inject advertisements in the cluttered urban space. Now, in 2015 screens are central to everyday life, but in a completely different way in respect to what had been imagined. Through ubiquitous computing and social media, information is abundant. Digital technologies have changed the way people relate to cities supporting discussion on multiple levels, allowing citizens to be more vocal than ever before. We question how architects can use the affordances of urban informatics to obtain and navigate useful social information to inform design. This chapter investigates different approaches to engage communities in the debate on cities, in particular it aims to capture citizens’ opinions on the use and design of public places. Physical and digital discussions have been initiated to capture citizens’ opinions on the use and design of public places. In addition to traditional consultation methods, Web 2.0 platforms, urban screens, and mobile apps are used in the context of Brisbane, Australia to explore contemporary strategies of engagement (Gray 2014).

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Root system traits of Norway spruce, Scots pine, and silver birch in mixed boreal forests: an analysis of root architecture, morphology, and anatomy

The aim of this thesis was to unravel the functional-structural characteristics of root systems of Betula pendula Roth., Picea abies (L.) Karst., and Pinus sylvestris L. in mixed boreal forest stands differing in their developmental stage and site fertility. The root systems of these species had similar structural regularities: horizontally-oriented shallow roots defined the horizontal area of influence, and within this area, each species placed fine roots in the uppermost soil layers, while sinker roots defined the maximum rooting depth. Large radial spread and high ramification of coarse roots, and the high specific root length (SRL) and root length density (RLD) of fine roots indicated the high belowground competitiveness and root plasticity of B. pendula. Smaller radial root spread and sparser branching of coarse roots, and low SRL and RLD of fine roots of the conifers could indicate their more conservative resource use and high association with and dependence on ectomycorrhiza-forming fungi. The vertical fine root distributions of the species were mostly overlapping, implying the possibility for intense belowground competition for nutrients. In each species, conduits tapered and their frequency increased from distal roots to the stem, from the stem to the branches, and to leaf petioles in B. pendula. Conduit tapering was organ-specific in each species violating the assumptions of the general vascular scaling model (WBE). This reflects the hierarchical organization of a tree and differences between organs in the relative importance of transport, safety, and mechanical demands. The applied root model was capable of depicting the mass, length and spread of coarse roots of B. pendula and P. abies, and to the lesser extent in P. sylvestris. The roots did not follow self-similar fractal branching, because the parameter values varied within the root systems. Model parameters indicate differences in rooting behavior, and therefore different ecophysiological adaptations between species.

Determinants of Cognitive Impairment in Old Age and Their Genetic Architecture

Cognitive health is of central importance for independent and balanced old age, while memory disorders represent the leading cause of intensive and long-term care among the Finnish elderly. The aims of this study were to analyse the effect of height, body mass index, weight change, metabolic conditions and coffee drinking in midlife on cognitive performance in old age among a sample of 2606 Finnish twins aged 65 years or older who had participated in a telephone interview to assess their cognitive status. Since coffee drinking associates with several metabolic conditions and Finns are known to be the greatest consumers of coffee in the world, the heritability and stability of coffee drinking was analysed in the whole Older Finnish Twin Cohort (n=10716). In order to investigate the association between height and cognitive performance in a population with more supportive childhood living conditions, a total of 2161 Danish twins were included in this study. A greater height was found to clearly associate with better cognitive performance in Finnish subjects, but less so among the Danish sample, which may reflect the childhood environmental differences between these cohorts. In the Finnish subjects, there was greater variance in cognitive performance among shorter subjects, and environmental factors were found to play a greater role in their cognitive performance, whereas the cognitive performance of taller participants was mainly explained by genetic factors. Midlife metabolic variables that were found to be significantly associated with a poorer cognitive performance in old age included a higher body mass index and three metabolic conditions: cardiovascular disease, hypertension and, most significantly of all, diabetes. Moreover, both weight gain and loss, even to a lesser degree than suggested previously, were found to be associated with poorer cognition. Furthermore, evidence of a causal relationship between midlife cardiovascular disease and cognitive performance in old age was demonstrated among discordant twin pairs. Conversely, no effect of coffee drinking in midlife on cognitive performance in old age was observed, although coffee drinking was demonstrated to be stable in the study population. The heritability of coffee drinking was found to differ across sexes and age groups, being 51% in men and 52% in women in the whole study population. This study supports the contention that cognitive performance in old age reflects the effects of multiple genetic and environmental exposures, including their complex interactions during the life-span. The demonstrated associations and evidence of a causal pathway between potentially preventable exposures and poorer cognitive performance highlight the importance of preventive medicine.

Enterprise architecture – the foundation for a strategy

Artikkeli selostaa kokonaisarkkitehtuurin käsitettä ja Kansallinen digitaalinen kirjasto -hankkeen kokonaisarkkitehtuurin laatimista. Kokonaisarkkitehtuuri on tietohallinnon strategisen suunnittelun ja johtamisen väline, mutta sillä on monia käytännöllisempia käyttötarkoituksia esimerkiksi tietojärjestelmien kehittämisessä. Kansallinen digitaalinen kirjasto on opetus- ja kulttuuriministeriön tavoitteena on varmistaa kulttuurin ja tieteen digitaalisten tietovarantojen tehokas ja laadukas hallinta, jakelu ja pitkäaikaissäilytys. Lisäksi hankkeessa edistetään kulttuuriperintö- ja asiakirja-aineistojen digitointia.

Parallel min-cut placement on reduced hardware SIMD architecture.

Massively parallel SIMD computing is applied to obtain an order of magnitude improvement in the executional speed of an important algorithm in VLSI design automation. The physical design of a VLSI circuit involves logic module placement as a subtask. The paper is concerned with accelerating the well known Min-cut placement technique for logic cell placement. The inherent parallelism of the Min-cut algorithm is identified, and it is shown that a parallel machine based on the efficient execution of the placement procedure.