Design and Fabrication of a Photonic Crystal Channel Drop Filter Based on an Asymmetric Silicon-on-Insulator Slab

We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.

Experimental Demonstration on Structure-Parameter Dependence of Photonic Crystal Optical Spectrum

We present fabrication and experimental measurement of a series of photonic crystal waveguides and coupled structure of PC waveguide and PC micro-cavity. The complete devices consist of an injector taper down from 3 mu m into a triangular-lattice air-holes single-line-defect waveguide. We fabricated these devices on a silicon-on-insulator substrate and characterized them using tunable laser source. We've obtained high-efficiency light propagation and broad flat spectrum response of photonic-crystal waveguides. A sharp attenuation at photonic crystal waveguide mode edge was observed for most structures. The edge of guided band is shifted about 31 nm with the 10 nm increase of lattice constant. Mode resonance was observed in coupled structure. Our experimental results indicate that the optical spectra of photonic crystal are very sensitive to structure parameters.

Theoretical and Experimental Studies of an Ultra-compact Photonic Crystal Corner Mirror Based on Silicon-On-Insulator

An ultra-compact silicon-on-insulator based photonic crystal corner mirror is designed and optimized. A sample is then successfully fabricated with extra losses 1.1 +/- 0.4dB for transverse-electronic (M) polarization for wavelength range of 1510-1630nm.

Fabrication and characterization of two-dimensional photonic crystal on silicon by efficient methods

Two-dimensional photonic crystals working in near infrared region are fabricated into silicon-on-insulator wafer by 248-nm deep UV lithography. We present an efficient way to measure the photonic crystal waveguide's light transmission spectra at given polarization states.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

SOI optical switch matrix integrated with spot size converter (SSC) and total internal reflection (TIR) mirrors

SOI (Silicon on Insulator) based photonic devices has attracted more and more attention in the recent years. Integration of SOI optical switch matrix with isolating grooves, total internal reflection (TIR) mirrors and spot size converter (SSC) was studied. A folding re-arrangeable non-blocking 4x4 optical switch matrix and a blocking 16x16 matrix with TIR mirrors and SSC were fabricated on SOI wafer. The performaces, including extinction ratio and the crosstalk, are better than before. The insertion loss and the polarization dependent loss (PDL) at 1.55 mu m increase slightly with longer device length, more bend and intersecting waveguides. The insertion losses decrease 2 similar to 3 dB when anti-reflection films are added in the ends of the devices. The rise and fall times of the devices are 2.1 mu s and 2.3 mu s, respectively.

Two-dimensional photonic crystals with a large photonic band gap designed by a rapid genetic algorithm

We used Plane Wave Expansion Method and a Rapid Genetic Algorithm to design two-dimensional photonic crystals with a large absolute band gap. A filling fraction controlling operator and Fourier transform data storage mechanism had been integrated into the genetic operators to get desired photonic crystals effectively and efficiently. Starting from randomly generated photonic crystals, the proposed RGA evolved toward the best objectives and yielded a square lattice photonic crystal with the band gap (defined as the gap to mid-gap ratio) as large as 13.25%. Furthermore, the evolutionary objective was modified and resulted in a satisfactory PC for better application to slab system.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

A CMOS front-end circuit for SONET OC-96 receiver

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mu m CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2GHz bandwidth for 0.5pF photodiode (PD) capacitance and 1.2k 0 transimpedance gain. The LA achieved 5.4GHz bandwidth and 29dB voltage gain. The optical sensitivity is -19dBm at 5-Gb/s for a bit-error rate of 10(-12), and it dissipates 45.5mW for I.8V supply.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Electroabsorption modulated semiconductor optical amplifier monolithically integrated with spot-size converters

We have demonstrated an electroabsorption modulator (EAM) and semiconductor optical amplifier (SOA) monolithically integrated with novel dual-waveguide spot-size converters (SSCs) at the input and output ports for low-loss coupling to planar light-guide circuit silica waveguide or cleaved single-mode optical fiber. The device is fabricated by means of selective-area MOVPE growth (SAG), quantum well intermixing (QWI) and asymmetric twin waveguide (ATG) technologies with only three steps low-pressure MOVPE growth. For the device structure, in SOA/EAM section, double ridge structure was employed to reduce the EAM capacitances and enable high bit-rate operation. In the SSC sections, buried ridge stripe (BRS) were incorporated. Such a combination of ridge, ATG and BRS structure is reported for the first time in which it can take advantage of both easy processing of ridge structure and the excellent mode characteristic of BRS. At the wavelength range of 1550-1600 nm, lossless operation with extinction ratios of 25 dB DC and more than 10 GHz 3-dB bandwidth is successfully achieved. The beam divergence angles of the input and output ports of the device are as small as 8.0 degrees x 12.6 degrees, resulting in 3.0 dB coupling loss with cleaved single-mode optical fiber. (c) 2005 Elsevier B.V. All rights reserved.

A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

Fabrication of a novel silica PLC hybrid integrated triplexer

A new-style silica planar lightwave circuit (PLC) hybrid integrated triplexer, which can demultiplex 1490-nm download data and 1550-nm download analog signals, as well as transmit 1310-nm upload data, is presented. It combines SiO2 arrayed waveguide gratings (AWGs) with integrated photodetectors (PDs) and a high performance laser diode (LD). The SiO2 AWGs realize the three-wavelength coarse wavelength-division multiplexing (CWDM). The crosstalk is less than 40 dB between the 1490- and 1550-nm channels, and less than 45 dB between 1310- and 1490- or 1550-nm channels. For the static performances of the integrated triplexer, its upload output power is 0.4 mW, and the download output photo-generated current is 76 A. In the small-signal measurement, the upstream 3-dB bandwidth of the triplexer is 4 GHz, while the downstream 3-dB bandwidths of both the analog and digital sections reach 1.9 GHz.