Mach-Zehnder interferometers with asymmetric modulation arms in applications of high speed silicon-on-insulator based optical switches

Modulation arms with different widths are introduced to Mach-Zehnder interferometers (MZIs) to obtain improved performance. Theoretical analysis and numerical simulation have shown that when the widths of the two arms are properly designed to achieve an inherent m pi/2 (m is an odd integer) optical phase difference between the arms, the asymmetric MZI presents higher modulation speed. Furthermore, the carrier-absorption induced divergence of insertion losses in silicon-on-insulator (SOI) based MZI optical switches can be obviously improved.

Size tolerance analysis of a 4X4 tapered multimode interference coupler in a silicon-on-insulator structure

Size tolerance of a 4X4 general interference tapered multimode interference (MMI) coupler in a silicon-on-insulator (SOI) structure is investigated by means of a 2-D finite difference beam propagation method (2D-FDBPM), together with an effective refractive index method (EIM). The results show that the tapered multimode interference coupler exhibits relatively larger size tolerance when light is launched from the edgeport than from midport, though it has much better output power uniformity when light is launched from midport. Besides that, it can reduce the device length greatly. The 4X4 general interference tapered MMI coupler has a slightly larger size tolerance compared with a conventional straight multimode interference coupler. (C) 2003 Society of Photo-Optical Instrumentation Engineers.

Improving response speed of electrooptical switch in silicon-on-insulator by modifying modulation area structure

This paper reports on the simulation of two 2 x 2 electrooptical switches with different modulation area structures in silicon-on-insulator (SOI). A two-dimensional (2D) semiconductor device simulation tool PISCES-II has been used to analyze the dc and transient behaviors of the two devices. The modeling results show that the switch with an N+-I-P+-I-N+ modulation structure has a much faster response speed than the device with a P+-I-N+ modulation structure, although the former requires slightly stronger injection power.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

The new exploration for proton-implanted silicon: the conversion of a surface-region-purification-induced p-n junction into a p-i-n electrical structure approaching silicon on insulator

A surface-region-purification-induced p-n junction, a puzzle discovered at Brookhaven National Laboratory, in a silicon-on-defect-layer (SODL) material has been explored by carrying out various annealing conditions and subsequent measurements on electrical properties. The origin of the pn junction has been experimentally investigated. Furthermore, the p-n junction has been transformed into a p-i-n electrical structure by adding a high temperature annealing process to the previously used SODL procedure, making the SODL material approach silicon on insulator (SOI). The control of the initial oxygen amount in the silicon material is suggested to be critical for the experimental results.

High efficiency fiber to waveguide optical coupler in silicon-on-insulator-based slot waveguides - art. no. 68310R

We propose a novel optical fiber-to-waveguide coupler for integrated optical circuits. The proper materials and structural parameters of the coupler, which is based on a slot waveguide, are carefully analyzed using a full-vectorial three dimensional mode solver. Because the effective refractive index of the mode in a silicon-on-insulator-based slot waveguide can be extremely close to that of the fiber, a highly efficient fiber-to-waveguide coupling application can be realized. For a TE-like mode, the calculated minimum mismatch loss is about 1.8dB at 1550nm, and the mode conversion loss can be less than 0.5dB. The discussion of the present state-of-the-art is also involved. The proposed coupler can be used in chip-to-chip communication.

Design and Fabrication of a Photonic Crystal Channel Drop Filter Based on an Asymmetric Silicon-on-Insulator Slab

We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.

Effect of Silicon-on-Insulator Substrate on Residual Strain in 3C-SiC Films

One group of SiC films are grown on silicon-on-insulator （SOI） substrates with a series of silicon-overlayer thickness. Raman scattering spectroscopy measurement clearly indicates that a systematic trend of residual stress reduction as the silicon over-layer thickness decreases for the SOI substrates. Strain relaxation in the SiC epilayer is explained by force balance approach and near coincidence lattice model.

Integrated MMI Optical Couplers and Optical Switches in Silicon-on-Insulator Technology

Integrated multimode interference (MMI) coupler based on silicon-on-insulator(SOI) has been becoming a kind of more and more attractive device in optical systems. SiO2thin cladding layers (＜1.0 μm) can be usedin SOI waveguide due to the large index step be-tween Si and SiO2, making them compatible with VLSI technology. The design and fabrica-tion of MMI optical couplers and optical switches in SOI technology are presented in thepa-per. We demonstrated the switching time of 2 × 2 MMI-MZI thermo-optical switch is less than 20 μs:

Integrated tapered MMI couplers in the silicon-on-insulator technology

The authors have designed and fabricated 2x2 parabolically tapered MMI coupler with large cross-section and large space between difference ports using Silicon-on-Insulator ( SOI) technology. The devices demonstrate a minimum uniformity of 0.8dB and 30% shorter than the straight MMI coupler.

Integrated multimode interference couplers in silicon-on insulator

Silicon-on insulator (SOI) is an attractive platform for the fabrication of optoelectronic integrated circuit. Thin cladding layers (< 1.0m) can be used in SOI waveguide due to the large index step between Si and SiO2, making them compatible with the VLSI technology. Here we demonstrate the fabrication of 1 x 4 and 2 x 2 multimode interference (MMI) coupler based on SOI technology. Performances of the devices are analyzed. The minimum excess loss of the devices is about 1.8dB. The devices show uniform power distribution.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Characterization of integrated Bragg gratings in silicon-on-insulator

Silicon-on-insulator (SOI) is rapidly emerging as a very promising material platform for integrated photonics. As it combines the potential for optoelectronic integration with the low-cost and large volume manufacturing capabilities and they are already accumulate a huge amount of applications in areas like sensing, quantum optics, optical telecommunications and metrology. One of the main limitations of current technology is that waveguide propagation losses are still much higher than in standard glass-based platform because of many reasons such as bends, surface roughness and the very strong optical confinement provided by SOI. Such high loss prevents the fabrication of efficient optical resonators and complex devices severely limiting the current potential of the SOI platform. The project in the first part deals with the simple waveguides loss problem and trying to link that with the polarization problem and the loss based on Fabry-Perot Technique. The second part of the thesis deals with the Bragg Grating characterization from again the point of view of the polarization effect which leads to a better stop-band use filters. To a better comprehension a brief review on the basics of the SOI and the integrated Bragg grating ends up with the fabrication techniques and some of its applications will be presented in both parts, until the end of both the third and the fourth chapters to some results which hopefully make its precedent explanations easier to deal with.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

A two-dimensional photonic crystal slab mirror with silicon on insulator for wavelength 1.3 mu m

A concrete two-dimensional photonic crystal slab with triangular lattice used as a mirror for the light at wavelength 1.3 mu m with a silicon-on-insulator (Sol) substrate is designed by the three-dimensional plane wave expansion method. For TE-like modes, the bandgap in the F-K direction is from 1087nm to 1559nm. The central wavelength in the bandgap is about 1.3 mu m, hence the incident light at wavelength 1.3 mu m will be strongly reflected. Experimentally, such a photonic crystal slab is fabricated on an SOI substrate by the combination of EBL and ICP etching. The measurement of its transmission characteristics shows the bandgap edge in a longer wavelength is about 1540mn. The little discrepancy between the experimental data and the theoretical values is mainly due to the size discrepancy of the fabricated air holes.