Solution-processed dual-gate polymer field-effect transistors for display applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Improved performance in diketopyrrolopyrrole-based transistors with bilayer gate dielectrics

There has been significant progress in the past 2 decades in the field of organic and polymer thin-film transistors. In this paper, we report a combination of stable materials, device architecture, and process conditions that resulted in a patterned gate, small channel length (<5 μm) device that possesses a scaled field-induced conductivity in air that is higher than any organic/polymer transistor reported thus far. The operating voltage is below 10 V; the on-off ratio is high; and the active materials are solution-processable. The semiconducting polymer is a new donor-acceptor polymer with furan-substituted diketopyrrolopyrrole and thienyl-vinylene-thienyl building blocks in the conjugated backbone. One of the major striking features of our work is that the patterned-gate device architecture is suitable for practical applications. We also propose a figure of merit to meaningfully compare polymer/organic transistor performance that takes into account mobility and operating voltage. With this figure of merit, we compare leading organic and polymer transistors that have been hitherto reported. The material and device architecture have shown very high mobility and low operating voltage for such short channel length (below 5 μm) organic/polymer transistors.

Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.

Lock the gate: Fracking, investor-state dispute settlement, and the Trans-Pacific Partnership

There has been much debate about the relationship between international trade, the environment, biodiversity protection, and climate change.The Obama Administration has pushed such issues into sharp relief, with its advocacy for sweeping international trade agreements, such as the Trans-Pacific Partnership and the Trans-Atlantic Trade and Investment Partnership. There has been much public concern about the impact of the mega-trade deals upon the protection of the environment. In particular, there has been a debate about whether the Trans-Pacific Partnership will promote dirty fracking. Will the Trans-Pacific Partnership transform the Pacific Rim into a Gasland?There has been a particular focus upon investor-state dispute settlement being used by unconventional mining companies. Investor-state dispute settlement is a mechanism which enables foreign investors to seek compensation from national governments at international arbitration tribunals. In her prescient 2009 book, The Expropriation of Environmental Governance, Kyla Tienhaara foresaw the rise of investor-state dispute resolution of environmental matters. She observed:'Over the last decade there has been an explosive increase of cases investment arbitration. This is significant in terms of not only the number of disputes that have arisen and the number of states that have been involved, but also the novel types of dispute that have emerged. Rather than solely involving straightforward incidences of nationalization or breach of contract, modern disputes often revolve around public policy measures and implicate sensitive issues such as access to drinking water, development on sacred indigenous sites and the protection of biodiversity.'In her study, Kyla Tienhaara observed that investment agreements, foreign investment contracts and investment arbitration had significant implications for the protection for the protection of the environment. She concluded that arbitrators have made it clear that they can, and will, award compensation to investors that claim to have been harmed by environmental regulation. She also found that some of the cases suggest that the mere threat of arbitration is sufficient to chill environmental policy development. Tienhaara was equally concerned by the possibility that a government may use the threat of arbitration as an excuse or cover for its failure to improve environmental regulation. In her view, it is evident that arbitrators have expropriated certain fundamental aspects of environmental governance from states. Tienhaara held: As a result, environmental regulation has become riskier, more expensive, and less democratic, especially in developing countries. This article provides a comparative analysis of the battles over fracking, investment, trade, and the environment in a number of key jurisdictions including the United States, Canada, Australia, and New Zealand. Part 1 focuses upon the United States. Part 2 examines the dispute between the Lone Pine Resources Inc. and the Government of Canada over a fracking moratorium in Quebec. Part 3 charts the rise of the Lock the Gate Alliance in Australia, and its demands for a moratorium in respect of coal seam gas and unconventional mining. Part 4 focuses upon parallel developments in New Zealand. This article concludes that Pacific Rim countries should withdraw from investor-state dispute settlement procedures, because of the threat posed to environmental regulation in respect of air, land, and water.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ``crossover point''). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

Garden gate to Daijas' father's house Architecture; Residences; Exterior

Verso: Das Gartentor zu Daijas Vaterhaus Georg lebete um die Ecke

Effect of organic gate dielectric material properties on interfacial charging and discharging of pentacene MIM device

The effect of material properties of an environmentally friendly, optically transparent dielectric material, polyterpenol, on the carrier transients within the pentacene-based double-layer MTM device was investigated. Polyterpenol films were RF plasma polymerised under varied process conditions, with resultant films differing in surface chemistry and morphology. Independent of type of polyterpenol, time-resolved EFISHG study of IZO/polyterpenol/pentacene/Au structures showed similar transient behaviour with carriers injected into pentacene from Au electrode only, confirming polyterpenol to be a suitable blocking layer for visualisation of single-species carrier transportation during charging and discharging under different bias conditions. Polyterpenol fabricated under higher input power show better promise due to higher chemical and thermal stability, improved uniformity, and absence of defects.

Jer. (Jerusalem) - Temple Pl. (place) - Golden Gate

Digital image

Entrance Gate to Old City of Jerusalem

Digital image

The Gate, Internment camp at Huyton, near Liverpool.

Signed and dated lower right. See also 78.1689

RF Sputtered Er2O3 Thin Films as High-k Gate Dielectrics for Germanium MOS Devices

We report the material and electrical properties of Erbium Oxide (Er2O3) thin films grown on n-Ge (100) by RF sputtering. The properties of the films are correlated with the processing conditions. The structural characterization reveals that the films annealed at 550 degrees C, has densified as compared to the as-grown ones. Fixed oxide charges and interface charges, both of the order of 10(13)/cm(2) is observed.

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.