Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.