Quantum mechanical simulation of nanosized metal-oxide-semiconductor field-effect transistor using empirical pseudopotentials: A comparison for charge density occupation methods

The atomistic pseudopotential quantum mechanical calculations are used to study the transport in million atom nanosized metal-oxide-semiconductor field-effect transistors. In the charge self-consistent calculation, the quantum mechanical eigenstates of closed systems instead of scattering states of open systems are calculated. The question of how to use these eigenstates to simulate a nonequilibrium system, and how to calculate the electric currents, is addressed. Two methods to occupy the electron eigenstates to yield the charge density in a nonequilibrium condition are tested and compared. One is a partition method and another is a quasi-Fermi level method. Two methods are also used to evaluate the current: one uses the ballistic and tunneling current approximation, another uses the drift-diffusion method. (C) 2009 American Institute of Physics. [doi:10.1063/1.3248262]

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

In situ doping control for growth of n-p-n Si/SiGe/Si heterojunction bipolar transistor by gas source molecular beam epitaxy

N-p-n Si/SiGe/Si heterostructures have been grown by a disilane (Si2H6) gas and Ge solid sources molecular beam epitaxy system using phosphine (PH3) and diborane (B2H6) as n- and p-type in situ doping sources, respectively. Adopting an in situ doping control technology, the influence of background B dopant on the growth of n-Si emitter layer was reduced, and an abrupt B dopant distribution from SiGe base to Si emitter layer was obtained. Besides, higher n-type doping in the surface region of emitter to reduce the emitter resist can be realized, and it did not result in the drop of growth rate of Si emitter layer in this technology. (C) 2004 Elsevier B.V. All rights reserved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A base-emitter self-aligned multi-finger Si1-xGex/Si power heterojunction bipolar transistor

With a crystal orientation dependent on the etch rate of Si in KOH-based solution, a base-emitter self-aligned large-area multi-linger configuration power SiGe heterojunction bipolar transistor (HBT) device (with an emitter area of about 880 mu m(2)) is fabricated with 2 mu m double-mesa technology. The maximum dc current gain is 226.1. The collector-emitter junction breakdown voltage BVCEO is 10 V and the collector-base junction breakdown voltage BVCBO is 16 V with collector doping concentration of 1 x 10(17) cm(-3) and thickness of 400 nm. The device exhibited a maximum oscillation frequency f(max) of 35.5 GHz and a cut-off frequency f(T) of 24.9 GHz at a dc bias point of I-C = 70 mA and the voltage between collector and emitter is V-CE = 3 V. Load pull measurements in class-A operation of the SiGe HBT are performed at 1.9 GHz with input power ranging from 0 dBm to 21 dBm. A maximum output power of 29.9 dBm (about 977 mW) is obtained at an input power of 18.5 dBm with a gain of 11.47 dB. Compared to a non-self-aligned SiGe HBT with the same heterostructure and process, f(max) and f(T) are improved by about 83.9% and 38.3%, respectively.

Quantum measurement characteristics of a double-dot single electron transistor

Owing to a few unique advantages, the double-dot single electron transistor has been proposed as an alternative detector for charge states. In this work, we present a further study for its signal-to-noise property, based on a full analysis of the setup configuration symmetry. It is found that the effectiveness of the double-dot detector can approach that of an ideal detector, if the symmetric capacitive coupling is taken into account. The quantum measurement efficiency is also analyzed by comparing the measurement time with the measurement-induced dephasing time.

Novel hybrid voltage controlled ring oscillators using single electron and MOS transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.

Design of two-dimensional photonic crystal edge emitting laser for photonic integrated circuits

An edge emitting laser based on two-dimensional photonic crystal slabs is proposed. The device consists of a square lattice microcavity, which is composed of two structures with the same period but different radius of air-holes, and a waveguide. In the cavity, laser resonance in the inner structure benelits from not only the anomalous dispersion characteristic of the first band-edge at the M point in the first Brillouin-zone but also zero photon states in the outer structure. A line defect waveguide is introduced in the outer structure for extracting photons from the inner cavity. Three-dimensional finite-difference time-domain simulations apparently show the in-plane laser output from the waveguide. The microcavity has an effective mode volume of about 3.2(lambda/eta(slab))(3) for oscillation -mode and the quality factor of the device including line defect waveguide is estimated to be as high as 1300.

A bistable, self-latching inverter by the monolithic integration of resonant tunnelling diode and high electron mobility transistor

This paper reports that the structures of AlGaAs/InGaAs high electron mobility transistor (HEMT) and AlAs/GaAs resonant tunnelling diode (RTD) are epitaxially grown by molecular beam epitaxy ( MBE) in turn on a GaAs substrate. An Al0.24Ga0.76As chair barrier layer, which is grown adjacent to the top AlAs barrier, helps to reduce the valley current of RTD. The peak-to-valley current ratio of fabricated RTD is 4.8 and the transconductance for the 1-mu m gate HEMT is 125mS/mm. A static inverter which consists of two RTDs and a HEMT is designed and fabricated. Unlike a conventional CMOS inverter, the novel inverter exhibits self-latching property.

Correlation between optical and electrical properties in In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor structures on GaAs substrates

4.2 K photoluminescence (PL) and 77 K standard Hall-effect measurements were performed for In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor (HEMT) structures grown on GaAs substrates with different indium contents in the InxGa1-xAs well or different Si delta-doping concentrations. It was found that electron concentrations increased with increasing PL intensity ratio of the "forbidden" transition (the second electron subband to the first heavy-hole subband) to the sum of the "allowed" transition (the first electron subband to the first heavy-hole subband) and the forbidden transition. And electron mobilities decreased with increasing product of the average full width at half maximum of allowed and forbidden transitions and the electron effective mass in the InxGa1-xAs quantum well. These results show that PL measurements are a good supplemental tool to Hall-effect measurements in optimization of the HEMT layer structure. (c) 2006 American Institute of Physics.

Zero-field spin splitting in In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor structures on GaAs substrates using Shubnikov-de Haas measurements

Shubnikov-de Haas measurements were carried out for In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor structures grown on GaAs substrates with different indium contents and/or different Si delta-doping concentrations. Zero-field (B-->0) spin splitting was found in samples with stronger conduction band bending in the InGaAs well. It was shown that the dominant spin splitting mechanism is attributed to the contribution by the Rashba term. We found that zero-field spin splitting not only occurs in the ground electron subband, but also in the first excited electron subband for a sample with Si delta-doping concentration of 6x10(12) cm(-2). We propose that this In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor structure grown on GaAs may be a promising candidate spin-polarized field-effect transistors. (C) 2002 American Institute of Physics.

Rapid thermal annealing effects on step-graded InAlAs buffer layer and In0.52Al0.48As/In0.53Ga0.47As metamorphic high electron mobility transistor structures on GaAs substrates

A step-graded InAlAs buffer layer and an In0.52Al0.48As/In0.53Ga0.47As metamorphic high electron mobility transistor (MM-HEMT) structures were grown by molecular beam epitaxy on GaAs (001) substrates, and rapid thermal annealing was performed on them in the temperature range 500-800 degreesC for 30 s. The as-grown and annealed samples were investigated with Hall measurements, and 77 K photoluminescence. After rapid thermal annealing, the resistivities of step-graded InAlAs buffer layer structures became high. This can avoid leaky characteristics and parasitic capacitance for MM-HEMT devices. The highest sheet carrier density n(s) and mobility mu for MM-HEMT structures were achieved by annealing at 600 and 650degreesC, respectively. The relative intensities of the transitions between the second electron subband to the first heavy-hole subband and the first electron subband to the first heavy-hole subband in the MM-HEMT InGaAs well layer were compared under different annealing temperatures. (C) 2002 American Institute of Physics.

Longitudinal optic phonon-plasmon coupling in delta-doped metamorphic InAlAs/InGaAs high-electron-mobility transistor structures on GaAs substrates

InAlAs/InGaAs metamorphic high-electron-mobility transistor structures with different spacer layers on GaAs substrates are characterized by Raman measurements. The influence of In0.52Al0.48As spacer thickness on longitudinal optic phonon-plasmon coupling is investigated. It is found that the intensity of GaAs-like longitudinal optic phonon, which couples with collective intersubband transitions of two-dimensional electron gas, is strongly affected by the different subband energy spacings, subband electron concentrations, and wave function distributions, which are determined by different spacer thicknesses. (C) 2001 American Institute of Physics.

Growth of SiGe heterojunction bipolar transistor using Si2H6 gas and Ge solid sources molecular beam epitaxy

N-p-n Si/SiGe/Si heterostructure has been grown by a disilane (Si2H6) gas and Ge solid sources molecular beam epitaxy system using phosphine (PH3) and diborane (B2H6) as n- and p-type in situ doping sources, respectively. X-ray diffraction (XRD) and secondary ion mass spectroscopy (SIMS) measurements show that the grown heterostructure has a good quality, the boron doping is confined to the SiGe base layer, and the Ge has a trapezoidal profile. Postgrowth P implantation was performed to prepare a good ohmic contact to the emitter. Heterojunction bipolar transistor (HBT) has been fabricated using the grown heterostructure and a common-emitter current gain of 75 and a cut-off frequency of 20 GHz at 300 K have been obtained. (C) 2001 Elsevier Science B.V. All rights reserved.

The growth of Si/SiGe/Si structures for heterojunction bipolar transistor by gas source molecular beam epitaxy

Three n-p-n Si/SiGe/Si heterostructures with different layer thickness and doping concentration have been grown by a home-made gas source molecular-beam epitaxy (GSMBE) system using phosphine (PH3) and diborane (B2H6) as n-and p-type in situ doping sources, respectively. Heterojunction bipolar transistors (HBTs) have been fabricated using these structures and a current gain of 40 at 300 K and 62 at 77 K have been obtained. The influence of thickness and doping concentration of the deposited layers on the current gain of the HBTs is discussed. (C) 2000 Elsevier Science B.V. All rights reserved.