A frequency measure robust to linear filtering

It is noted that the determination of an oscillation frequency by used of the power spectrum of measured time series is susceptible to filtering of the signal. Similarly, frequency measurements made by period counting can yield different, results depending on how the signal is filtered for noise reduction. In an attempt to eliminate these ambiguities, a new measure of frequency, based on an approximate reconstruction of the phase-space trajectory of the oscillator from the signal, is introduced. This measure is shown to be invariant under linear filtering. For this reason, it is also inaccessible by spectral methods. The effect of filtering on frequency for weakly nonlinear, noisy oscillators, to which this definition applies only imperfectly, is quantified. This work provides the theoretical basis for frequency measurements employing MIRVA filtering.

Data-driven optimal filtering for phase and frequency of noisy oscillations: Application to vortex flow metering

A method for measuring the phase of oscillations from noisy time series is proposed. To obtain the phase, the signal is filtered in such a way that the filter output has minimal relative variation in the amplitude over all filters with complex-valued impulse response. The argument of the filter output yields the phase. Implementation of the algorithm and interpretation of the result are discussed. We argue that the phase obtained by the proposed method has a low susceptibility to measurement noise and a low rate of artificial phase slips. The method is applied for the detection and classification of mode locking in vortex flow meters. A measure for the strength of mode locking is proposed.

High contrast plasma mirror: spatial filtering and second harmonic generation at 10(19)Wcm(-2)

Recently, the use of plasma optics to improve temporal pulse contrast has had a remarkable impact on the field of high- power laser-solid density interaction physics. Opening an avenue to previously unachievable plasma density gradients in the high intensity focus, this advance has enabled researchers to investigate new regimes of harmonic generation and ion acceleration. Until now, however, plasma optics for fundamental laser reflection have been used in the sub-relativistic intensity regime (10(15) - 10(16)Wcm(-2)) showing high reflectivity (similar to 70%) and good focusability. Therefore, the question remains as to whether plasma optics can be used for such applications in the relativistic intensity regime (> 10(18)Wcm(-2)). Previous studies of plasma mirrors (PMs) indicate that, for 40 fs laser pulses, the reflectivity fluctuates by an order of magnitude and that focusability of the beam is lost as the intensity is increased above 5 x 10(16)Wcm(-2). However, these experiments were performed using laser pulses with a contrast ratio of similar to 10(7) to generate the reflecting surface. Here, we present results for PM operation using high contrast laser pulses resulting in a new regime of operation - the high contrast plasma mirror (HCPM). In this regime, pulses with contrast ratio > 10(10) are used to form the PM surface at > 10(19)Wcm(-2), displaying excellent spatial filtering, reflected near- field beam profile of the fundamental beam and reflectivities of 60 +/- 5%. Efficient second harmonic generation is also observed with exceptional beam quality suggesting that this may be a route to achieving the highest focusable harmonic intensities. Plasma optics therefore offer the opportunity to manipulate ultra-intense laser beams both spatially and temporally. They also allow for ultrafast frequency up-shifting without detrimental effects due to group velocity dispersion (GVD) or reduced focusability which frequently occur when nonlinear crystals are used for frequency conversion.

SVM Training Phase Reduction Using Dataset Feature Filtering for Malware Detection

N-gram analysis is an approach that investigates the structure of a program using bytes, characters, or text strings. A key issue with N-gram analysis is feature selection amidst the explosion of features that occurs when N is increased. The experiments within this paper represent programs as operational code (opcode) density histograms gained through dynamic analysis. A support vector machine is used to create a reference model, which is used to evaluate two methods of feature reduction, which are 'area of intersect' and 'subspace analysis using eigenvectors.' The findings show that the relationships between features are complex and simple statistics filtering approaches do not provide a viable approach. However, eigenvector subspace analysis produces a suitable filter.

Systolic building block for high performance recursive filtering

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware. © 1989 Kluwer Academic Publishers.

Pipelined two-port adaptor for wave digital filtering

The application of fine-grain pipelining techniques in the design of high-performance wave digital filters (WDFs) is described. The problems of latency in feedback loops can be significantly reduced if computations are organized most significant, as opposed to least significant, bit first and if the results are fed back as soon as they are formed. The result is that chips can be designed which offer significantly higher sampling rates than otherwise can be obtained using conventional methods. How these concepts can be extended to the more challenging problem of WDFs is discussed. It is shown that significant increases in the sampling rate of bit-parallel circuits can be achieved using most significant bit first arithmetic.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.