Ultralow noise field-effect transistor from multilayer graphene

We present low-frequency electrical resistance fluctuations, or noise, in graphene-based field-effect devices with varying number of layers. In single-layer devices, the noise magnitude decreases with increasing carrier density, which behaved oppositely in the devices with two or larger number of layers accompanied by a suppression in noise magnitude by more than two orders in the latter case. This behavior can be explained from the influence of external electric field on graphene band structure, and provides a simple transport-based route to isolate single-layer graphene devices from those with multiple layers. ©2009 American Institute of Physics

Approximate solution for the redistribution of impurities during second oxidation

The impurity profile for the second oxidation, used in MOST fabrication, has been obtained by Margalit et al. [1]. The disadvantage of this technique is that the accuracy of their solution is directly dependent on the computer time. In this article, an analytical solution is presented using the approximation of linearizing the second oxidation procedure.

Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

Modeling and Analysis of Noise Margin in SET Logic

In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH, etc.) and noise margin. Finally the noise immunity of SET logic is compared with current CMOS logic.

Analysis of Ridge-Loaded Folded-Waveguide Slow-Wave Structures for Broadband Traveling-Wave Tubes

An E-plane serpentine folded-waveguide slow-wave structure with ridge loading on one of its broad walls is proposed for broadband traveling-wave tubes (TWTs) and studied using a simple quasi-transverse-electromagnetic analysis for the dispersion and interaction impedance characteristics, including the effects of the beam-hole discontinuity. The results are validated against cold test measurements, an approximate transmission-line parametric analysis, an equivalent circuit analysis, and 3-D electromagnetic modeling using CST Microwave Studio. The effect of the structure parameters on widening the bandwidth of a TWT is also studied.

Quantum theoretic explanation of the Schwarz-Hora effect

Following the path-integral approach we show that the Schwarz-Hora effect is a one-electron quantum-mechanical phenomenon in that the de Broglie wave associated with a single electron is modulated by the oscillating electric field. The treatment brings out the crucial role played by the crystal in providing a discontinuity in the longitudinal component of the electric field. The expression derived for the resulting current density shows the appropriate oscillatory behaviour in time and distance. The possibility of there being a temporal counterpart of Aharonov-Bohm effect is briefly discussed in this context.

Heteroepitaxial Yba2cu3o7-X-Prba2cu3o7-X-Yba2cu3o7-X Weak Links Grown By Laser Deposition

Summary form only given. The authors have developed a controllable HTSC (high-temperature superconductor) weak-link fabrication process for producing weak links from the high-temperature superconductor YBa2Cu3O7-x (YBCO), using PrBa2Cu3O7-x (PBCO) as a lattice-matched semiconducting barrier layer. The devices obtained show current-voltage characteristics similar to those observed for low-temperature superconductor/normal-metal/superconductor (SNS) devices. The authors found good scaling of the critical currents Ic with area, A, and scaling of the resistances Rj with 1/A; the typical values of the IcRj product of 3.5 mV are consistent with traditional SNS behavior. The authors observed Shapiro steps in response to 100-GHz millimeter-wave radiation and oscillation of the DC supercurrent in a transverse magnetic field, thus demonstrating that both the AC and DC Josephson effects occur in these devices.

Effect of a linear potential variation on the gate of an FET

This correspondence aims at reporting the results of an analysis carried out to find the effect of a linear potential variation on the gate of an FET.

Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit

In this paper, we focus on the performance of a nanowire field-effect transistor in the ultimate quantum capacitance limit (UQCL) (where only one subband is occupied) in the presence of interface traps (D-it), parasitic capacitance (C-L), and source/drain series resistance (R-s,R-d), using a ballistic transport model and compare the performance with its classical capacitance limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely: 1) gate capacitance; 2) drain-current saturation; 3) subthreshold slope; and 4) scaling performance. To gain physical insights into these effects, we also develop a set of semianalytical equations. The key observations are as follows: 1) A strongly energy-quantized nanowire shows nonmonotonic multiple-peak C-V characteristics due to discrete contributions from individual subbands; 2) the ballistic drain current saturates better in the UQCL than in the CCL, both in the presence and absence of D-it and R-s,R-d; 3) the subthreshold slope does not suffer any relative degradation in the UQCL compared to the CCL, even with Dit and R-s,R-d; 4) the UQCL scaling outperforms the CCL in the ideal condition; and 5) the UQCL scaling is more immune to R-s,R-d, but the presence of D-it and C-L significantly degrades the scaling advantages in the UQCL.

Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

The role of Compton and Raman scattering in the quasar continuum

There are three ways in which an electromagnetic wave can undergo scattering in a plasma: (i) when the scattering of radiation occurs by a single electron, it is called Compton Scattering (CS); (ii) if it occurs by a longitudinal electron plasma mode, it is called Stimulated Raman Scattering (SRS), and (iii) if it occurs by a highly damped electron plasma mode, it is called Stimulated Compton Scattering (SCS). The non-thermal continuum of quasars is believed to be produced through the combined action of synchrotron and inverse Compton processes, which are essentially single-particle processes. Here, we investigate the role of SRS and SCS in the generation of continuum radiation from these compact objects. It is shown as an example that the complete spectrum of 3C 273 can be reproduced by suitably combining SCS and SRS. The differential contributions of SCS and SRS under different values of the plasma parameters are also calculated.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

High-Performance Metal-Insulator-Metal Capacitors Using Europium Oxide as Dielectric

We report the first demonstration of metal-insulator-metal (MIM) capacitors with Eu2O3 dielectric for analog and DRAM applications. The influence of different anneal conditions on the electrical characteristics of the fabricated MIM capacitors is studied. FG anneal results in high capacitance density (7 fF/mu m(2)), whereas oxygen anneal results in low quadratic voltage coefficient of capacitance (VCC) (194 ppm/V-2 at 100 kHz), and argon anneal results in low leakage current density (3.2 x 10(-8) A/cm(2) at -1 V). We correlate these electrical results with the surface chemical states of the films through X-ray photoelectron spectroscopy measurements. In particular, FG anneal and argon anneal result in sub-oxides, which modulate the electrical properties.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.