57 resultados para CMOS analog integrated circuit

em Biblioteca Digital da Produção Intelectual da Universidade de São Paulo (BDPI/USP)


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This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 mu m CMOS technology, requiring an active area of just 200 mu m x 200 mu m. Experimental results, with a full-scale output current of 700 mu A and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.

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Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.

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In this work, high-aligned single-walled carbon nanotube (SWCNT) forest have been grown using a high-density plasma chemical vapor deposition technique (at room temperature) and patterned into micro-structures by photolithographic techniques, that are commonly used for silicon integrated circuit fabrication. The SWCNTs were obtained using pure methane plasma and iron as precursor material (seed). For the growth carbon SWCNT forest the process pressure was 15 mTorr, the RF power was 250W and the total time of the deposition process was 3 h. The micropatterning processes of the SWCNT forest included conventional photolithography and magnetron sputtering for growing an iron layer (precursor material). In this situation, the iron layer is patterned and high-aligned SWCNTs are grown in the where iron is present, and DLC is formed in the regions where the iron precursor is not present. The results can be proven by Scanning Electronic Microscopy and Raman Spectroscopy. Thus, it is possible to fabricate SWCNT forest-based electronic and optoelectronic devices. (C) 2010 Elsevier B.V. All rights reserved.

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FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. (C) 2009 Elsevier Ltd. All rights reserved.

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A simple and easy approach to produce polymeric microchips with integrated copper electrodes for capacitively coupled contactless conductivity detection (CD) is described. Copper electrodes were fabricated using a printed circuit board (PCB) as an inexpensive thin-layer of metal. The electrode layout was first drawn and laser printed on a wax paper sheet. The toner layer deposited on the paper sheet was thermally transferred to the PCB surface working as a mask for wet chemical etching of the copper layer. After the etching step, the toner was removed with an acetonitrile-dampened cotton. A poly(ethylene terephthalate) (PET) film coated with a thin thermo-sensitive adhesive layer was used to laminate the PCB plate providing an insulator layer of the electrodes to perform CID measurements. Electrophoresis microchannels were fabricated in poly(dimethylsiloxane) (PDMS) by soft lithography and reversibly sealed against the PET film. These hybrid PDMS/PET chips exhibited a stable electroosmotic mobility of 4.25 +/- 0.04 x 10(-4) V cm(-2) s(-1), at pH 6.1, over fifty runs. Efficiencies ranging from 1127 to 1690 theoretical plates were obtained for inorganic cations.

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A secure communication system based on the error-feedback synchronization of the electronic model of the particle-in-a-box system is proposed. This circuit allows a robust and simple electronic emulation of the mechanical behavior of the collisions of a particle inside a box, exhibiting rich chaotic behavior. The required nonlinearity to emulate the box walls is implemented in a simple way when compared with other analog electronic chaotic circuits. A master/slave synchronization of two circuits exhibiting a rich chaotic behavior demonstrates the potentiality of this system to secure communication. In this system, binary data stream information modulates the bifurcation parameter of the particle-in-a-box electronic circuit in the transmitter. In the receiver circuit, this parameter is estimated using Pecora-Carroll synchronization and error-feedback synchronization. The performance of the demodulation process is verified through the eye pattern technique applied on the recovered bit stream. During the demodulation process, the error-feedback synchronization presented better performance compared with the Pecora-Carroll synchronization. The application of the particle-in-a-box electronic circuit in a secure communication system is demonstrated.

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We preserit a computational procedure to control art experimental chaotic system by applying the occasional proportional feedback (OPF) method. The method implementation uses the fuzzy theory to relate the variable correction to the necessary adjustment in the control parameter. As an application We control the chaotic attractors of the Chua circuit. We present file developed circuits and algorithms to implement this control in real time. To simplify the used procedure, we use it low resolution analog to digital converter compensated for a lowpass filter that facilitates similar applications to control other systems. (C) 2007 Elsevier Ltd. All rights reserved.

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This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

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In this work we present the fabrication and operation of incandescent microlamps for integrated optics applications. This microlamp emits white and infrared light from a chromium resistor embedded in a free-standing silicon oxynitride (SiO(x)N(y)) cantilever that can be coupled to an optical waveguide. In fact, the chromium resistor is sandwiched between layers of SiO(x)N(y) that isolate it from the atmosphere, while electric current heats the resistor to incandescent temperatures. The same SiO(x)N(y) material used in the microlamp fabrication is also used to produce the optical waveguides to allow a monolithic integration of light source and optical circuit. Front-side bulk micromachining of the silicon substrate in potassium hydroxide (KOH) solution is used to fabricate the cantilevers that thermally isolate the resistors from the substrate, thus reducing the heat transfer and the current required to light the lamp.

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This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SCI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. (C) 2009 Elsevier Ltd. All rights reserved.

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In this work the performance of graded-channel (CC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with CC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using CC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with CC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using CC devices can be reduced by a factor of 5, in comparison with a standard Sol MOSFET, without gain loss or linearity degradation. (C) 2008 Elsevier Ltd. All rights reserved.

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Independent studies have shown that the median raphe nucleus (MRN) and dorsal hippocampus (DH) are involved in the expression of contextual conditioned fear (CFC). However, studies that examine the integrated involvement of serotonergic mechanisms of the MRN-DH are lacking. To address this issue, a CFC paradigm was used to test whether the serotonergic projections from the MRN to DH can influence CFC. Serotoninergic drugs were infused either into the MRN or DH prior to testing sessions in which freezing and startle responses were measured in the same context where 6 h previously rats received footshocks. A reduction of serotonin (5-HT) transmission in the MRN by local infusions of the 5-HT(1A) agonist 8-hydroxy-2-(di-n-propylamino)-tetralin (8-OH-DPAT) decreased freezing in response to the context but did not reduce fear-potentiated startle. This pattern of results is consistent with the hypothesis that MRN serotonergic mechanisms selectively modulate the freezing response to the aversive context. As for the DH, a decrease in postsynaptic 5-HT receptor activity at projection areas has been proposed to be the main consequence of 5-HT(1A) receptor activation in the MIRN. Intra-DH injections of 8-OH-DPAT inhibited both the freezing and fear-potentiated startle response to the context. To reconcile these findings, an inhibitory mechanism may exist between the incoming 5-HT pathway from the MRN to DH and the neurons of the DH output to other structures. The DH-amygdala or medial prefrontal cortex projections could well be this output circuit modulating the expression of CFC as revealed by measurements of Fos immunoreactivity in these areas. (C) 2009 Elsevier B.V. All rights reserved.

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This article describes the design, implementation, and experiences with AcMus, an open and integrated software platform for room acoustics research, which comprises tools for measurement, analysis, and simulation of rooms for music listening and production. Through use of affordable hardware, such as laptops, consumer audio interfaces and microphones, the software allows evaluation of relevant acoustical parameters with stable and consistent results, thus providing valuable information in the diagnosis of acoustical problems, as well as the possibility of simulating modifications in the room through analytical models. The system is open-source and based on a flexible and extensible Java plug-in framework, allowing for cross-platform portability, accessibility and experimentation, thus fostering collaboration of users, developers and researchers in the field of room acoustics.

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Context. Analysis of ages and metallicities of star clusters in the Magellanic Clouds provide information for studies on the chemical evolution of the Clouds and other dwarf irregular galaxies. Aims. The aim is to derive ages and metallicities from integrated spectra of 14 star clusters in the Small Magellanic Cloud, including a few intermediate/old age star clusters. Methods. Making use of a full-spectrum fitting technique, we compared the integrated spectra of the sample clusters to three different sets of single stellar population models, using two fitting codes available in the literature. Results. We derive the ages and metallicities of 9 intermediate/old age clusters, some of them previously unstudied, and 5 young clusters. Conclusions. We point out the interest of the newly identified as intermediate/old age clusters HW1, NGC 152, Lindsay 3, Lindsay 11, and Lindsay 113. We also confirm the old ages of NGC 361, NGC 419, Kron 3, and of the very well-known oldest SMC cluster, NGC 121.

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We report the discovery by the CoRoT satellite of a new transiting giant planet in a 2.83 days orbit about a V = 15.5 solar analog star (M(*) = 1.08 +/- 0.08 M(circle dot), R(*) = 1.1 +/- 0.1 R(circle dot), T(eff) = 5675 +/- 80 K). This new planet, CoRoT-12b, has a mass of 0.92 +/- 0.07 M(Jup) and a radius of 1.44 +/- 0.13 R(Jup). Its low density can be explained by standard models for irradiated planets.