Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

The use of gate-to-drain capacitance (C-gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET's has been reviewed and demonstrated. By analyzing the change in C-gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (I-bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q(ot), through gate-to-substrate capacitance (C-gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device's structure. (C) 2001 Elsevier Science Ltd. All rights reserved.

A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement

A new method to extract MOSFET's threshold voltage VT by measurement of the gate-to-substrate capacitance C-gb of the transistor is presented. Unlike existing extraction methods based on I-V data, the measurement of C-gb does not require de drain current to now between drain and source thus eliminating the effects of source and drain series resistance R-S/D, and at the same time, retains a symmetrical potential profile across the channel. Experimental and simulation results on devices with different sizes are presented to justify the proposed method.

Simulation of interface states effect on the scanning capacitance microscopy measurement of p-n junctions

A two-dimensional numerical simulation model of interface states in scanning capacitance microscopy (SCM) measurements of p-n junctions is presented-In the model, amphoteric interface states with two transition energies in the Si band gap are represented as fixed charges to account for their behavior in SCM measurements. The interface states are shown to cause a stretch-out-and a parallel shift of the capacitance-voltage characteristics in the depletion. and neutral regions of p-n junctions, respectively. This explains the discrepancy between - the SCM measurement and simulation near p-n junctions, and thus modeling interface states is crucial for SCM dopant profiling of p-n junctions. (C) 2002 American Institute of Physics.

Dopant extraction from scanning capacitance microscopy measurements of p-n junctions using combined inverse modeling and forward simulation

This article proposes a more accurate approach to dopant extraction using combined inverse modeling and forward simulation of scanning capacitance microscopy (SCM) measurements on p-n junctions. The approach takes into account the essential physics of minority carrier response to the SCM probe tip in the presence of lateral electric fields due to a p-n junction. The effects of oxide fixed charge and interface state densities in the grown oxide layer on the p-n junction samples were considered in the proposed method. The extracted metallurgical and electrical junctions were compared to the apparent electrical junction obtained from SCM measurements. (C) 2002 American Institute of Physics.

Characteristics of small-signal capacitances of silicon-on-sapphire MOSFETs

The measured inter-electrode capacitances of silicon-on-sapphire (SOS) MOSFETs are presented and compared with simulation results. It is shown that the variations of capacitances with DC bias differ from those of bulk MOSFETs due to change in body potential variation of the SOS device resulting from electron-hole pair generation through impact ionisation.

Experimental investigation of interface states and photovoltaic effects on the scanning capacitance microscopy measurement for p-n junction dopant profiling

Controlled polishing procedures were used to produce both uniformly doped and p-n junction silicon samples with different interface state densities but identical oxide thicknesses. Using these samples, the effects of interface states on scanning capacitance microscopy (SCM) measurements could be singled out. SCM measurements on the junction samples were performed with and without illumination from the atomic force microscopy laser. Both the interface charges and the illumination were seen to affect the SCM signal near p-n junctions significantly. SCM p-n junction dopant profiling can be achieved by avoiding or correctly modeling these two factors in the experiment and in the simulation. (c) 2005 American Institute of Physics.

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.