The arithmetic of receiver scheduling for electronic support

In Electronic Support, it is well known that periodic search strategies for swept-frequency superheterodyne receivers (SHRs) can cause synchronisation with the radar it seeks to detect. Synchronisation occurs when the periods governing the search strategies of the SHR and radar are commensurate. The result may be that the radar is never detected. This paper considers the synchronisation problem in depth. We find that there are usually a finite number of synchronisation ratios between the radar’s scan period and the SHR’s sweep period. We develop three geometric constructions by which these ratios can be found and we relate them to the Farey series. The ratios may be used to determine the intercept time for any combination of scan and sweep period. This theory can assist the operator of an SHR in selecting a sweep period that minimises the intercept time against a number of radars in a threat emitter list.

A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture

We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed.

Implementation of a triple modular redundant FPGA based safety critical system for reliable software execution

This paper describes the implementation of a TMR (Triple Modular Redundant) microprocessor system on a FPGA. The system exhibits true redundancy in that three instances of the same processor system (both software and hardware) are executed in parallel. The described system uses software to control external peripherals and a voter is used to output correct results. An error indication is asserted whenever two of the three outputs match or all three outputs disagree. The software has been implemented to conform to a particular safety critical coding guideline/standard which is popular in industry. The system was verified by injecting various faults into it.