An FPGA architecture with configurable multiplier and carry units for improved arithmetic performance

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Autoria(s): Rajagopalan, K.; Sutton, P. R.

Data(s)	01/01/2001
Identificador	http://espace.library.uq.edu.au/view/UQ:96064
Publicador	The Association for Computing Machinery
Palavras-Chave	#EX #290902 Integrated Circuits #671201 Integrated circuits and devices
Tipo	Conference Paper