A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture
| Contribuinte(s) |
A. Hariz |
|---|---|
| Data(s) |
01/01/2006
|
| Resumo |
We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed. |
| Identificador |
http://espace.library.uq.edu.au/view/UQ:104443/UQ104443_OA.pdf |
| Idioma(s) |
eng |
| Publicador |
The International Society for Optical Engineering |
| Palavras-Chave | #E1 #291601 Arithmetic and Logic Structures #671202 Modules-special and attached processors |
| Tipo |
Conference Paper |