Beyond the shadow space: architecture as a professional and creative process; during and post-conflict.

Introduction

Much has been written about the impact of conflict on the physical nature of cities; most obviously perhaps the damage, destruction, defensive construction and spatial reconfigurations that evolve in times of conflict. Set within the context of Belfast, Northern Ireland, this paper will focus on three areas. First, a closer reading of the long-term physical impact of conflict, in particular, the spatial forms and practices that persist conceptually and culturally, and/or resist re-conceptualisation. Secondly, the effect of conflict on the nature of architectural practice itself, considering whether issues such as appointment and procurement impacted on architectural expectation and the context of operation. Thirdly, the effect of conflict on people, in particular in relation to creativity and hence the psyche of practice itself. This section will also identify the conditions that undermine or support design quality and creativity not only within times of conflict but also as society evolves out of the shadow space. 1
Twelve years on from the Peace Agreement,2 it may seem remarkable from an external perspective that Northern Ireland still needs to be reflecting on its troubled past. But the immediate post-conflict phase offered the communities of Northern Ireland place and time to experience ‘normal life’, begin to reconcile themselves to the hurt they experienced and start to reconfigure their relationships to one another. Indeed, it has often been expressed that probing the issues too much, at too early a phase, might in fact ‘Open old wounds without resolving anything’ and/or ‘Destabilise the already fragile political system.’3 This tendency not to deliberate or be too probing is therefore understandable and might be the reason why, for example, Northern Ireland's first Architecture and Built Environment policy, published in June, 2006, contains only one routine reference to ‘the Troubles’.

Clearly, however, there is a time in the development of a healthy, functioning society, when in order effectively to plan its future, it must also carry out a closer reading and deeper understanding of its past. As Maya Angelou puts it, ‘History, despite its wrenching pain/ Cannot be unlived, and if faced/ With courage, need not be lived again.’4

Increasingly, those within the creative arts sector and the built environment professions are showing interest in carrying out that closer reading, teasing out issues around conflict. This was led in part by the recent publication of the Troubles Archive by the Arts Council of Northern Ireland.5 Those involved in the academic or professional development of future generations of architects are also concerned about the relevance of a post-conflict condition. As a profession, if architects purport to be concerned with context, then the almost tangible socio-political circumstances and legacy of Northern Ireland does inevitably require direct eye contact. This paper therefore aims to bring the relationship between conflict and architectural practice in Northern Ireland into sharp focus, not to constrain or dull creative practice but to heighten its potential.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

A VLSI Architecture for Variable Block Size Video Motion Estimation

With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

High-performance 3D median filter architecture for medical image despeckling

A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.

The Design Process- Making It Relevant For Students

Within the ever-changing arenas of architectural design and education, the core element of architectural education remains: that of the design process. The consideration of how to design in addition to what to design presents architectural educators with that most constant and demanding challenge of how do we best teach the design process?

This challenge is arguably most acute at a student's early stages of their architectural education. In their first years in architecture, students will commonly concentrate on the end product rather than the process. This is, in many ways, understandable. A great deal of time, money and effort go into their final presentations. They believe that it is what is on the wall that is going to be assessed. Armed with new computer skills, they want to produce eye-catching graphics that are often no more than a celebration of a CAD package. In an era of increasing speed, immediacy of information and powerful advertising it is unsurprising that students want to race quickly to presenting an end-product.

Recognising that trend, new teaching methods and models were introduced into the second year undergraduate studio over the past two years at Queen's University Belfast, aimed at promoting student self-reflection and making the design process more relevant to the students. This paper will first generate a critical discussion on the difficulties associated with the design process before outlining some of the methods employed to help promote the following; an understanding of concept, personalisation of the design process for the individual student; adding realism and value to the design process and finally, getting he students to play to their strengths in illustrating their design process like an element of product. Frameworks, examples, outcomes and student feedback will all be presented to help illustrate the effectiveness of the new strategies employed in making the design process firstly, more relevant and therefore secondly, of greater value, to the architecture student.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Architecture, memory and historical continuity in Old Cairo

The hawari (local communities) of Old Cairo resemble a unique societal context whose history is actively involved in the contemporary everyday production of local habits, traditions and social practice. By the virtue of its durability and ability to survive, Architecture brings events and traditions of the past alive into the present through the spatial transformation, social practice and the value of the historical-fabric. The presence of buildings and houses from different historical periods has helped the local community’s memory to carry social practices over from one generation to another. This article explores the relationship between architecture, memory and everyday social practices through determining the way architecture moderates community experiences and communicates narratives among generations in haret al-Darb al-Asfar in old Cairo. Architecture emerges as a moderator of cross-time communication and as physical elements that help visualize history, situate values and materialize local traditions in old Cairo. Architecture, as process and product this article reports, works as agent of continuity, which in conjunction with the narrators, brings the full experience of the past alive in the present and helps guide future generations.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Simple trapped-ion architecture for high-fidelity Toffoli gates

We discuss a simple architecture for a quantum TOFFOLI gate implemented using three trapped ions. The gate, which, in principle, can be implemented with a single laser-induced operation, is effective under rather general conditions and is strikingly robust (within any experimentally realistic range of values) against dephasing, heating, and random fluctuations of the Hamiltonian parameters. We provide a full characterization of the unitary and noise-affected gate using three-qubit quantum process tomography.

Relational architecture description language for software families

Software Product-Line Engineering has emerged in recent years, as an important strategy for maximising reuse within the context of a family of related products. In current approaches to software product-lines, there is general agreement that the definition of a reference-architecture for the product-line is an important step in the software engineering process. In this paper we introduce ADLARS, a new form of architecture Description language that places emphasis on the capture of architectural relationships. ADLARS is designed for use within a product-line engineering process. The language supports both the definition of architectural structure, and of important architectural relationships. In particular it supports capture of the relationships between product features, component and task architectures, interfaces and parameter requirements.

Towards an automated evaluation process for software architectures

Optimizing and editing enterprise software systems, after the implementation process has started, is widely recognized to be an expensive process. This has led to increasing emphasis on locating mistakes within software systems at the design stage, to help minimize development costs. There is increasing interest in the field of architecture evaluation techniques that can identify problems at the design stage, either within complete, or partially complete architectures. Most current techniques rely on manual review-based evaluation methods that require advanced skills from architects and evaluators. We are currently considering what a formal Architecture Description Language (ADL) can contribute to the process of architecture evaluation and validation. Our investigation is considering the inter-relationships between the activities performed during the architecture evaluation process, the characteristics an ADL should possess to support these activities, and the tools needed to provide convenient access to, and presentation of architectural information.